From 4042138101d433cefed0a9157a2dc6fda54e4b60 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 14 Jul 2021 19:52:49 +0200
Subject: Add changes to Icarus for fuzzing

---
 src/Verismith/Verilog/Parser.hs | 34 +++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

(limited to 'src/Verismith/Verilog/Parser.hs')

diff --git a/src/Verismith/Verilog/Parser.hs b/src/Verismith/Verilog/Parser.hs
index 80996ba..a10fe22 100644
--- a/src/Verismith/Verilog/Parser.hs
+++ b/src/Verismith/Verilog/Parser.hs
@@ -32,6 +32,7 @@ import Data.Functor (($>))
 import Data.Functor.Identity (Identity)
 import Data.List (isInfixOf, isPrefixOf, null)
 import Data.List.NonEmpty (NonEmpty (..))
+import qualified Data.Map.Strict as Map
 import Data.Text (Text)
 import qualified Data.Text as T
 import qualified Data.Text.IO as T
@@ -521,6 +522,37 @@ parseModDecl = do
       modItem
       paramList
 
+mergeMaybe :: Maybe a -> Maybe a -> Maybe a
+mergeMaybe (Just a) Nothing = Just a
+mergeMaybe Nothing (Just a) = Just a
+mergeMaybe a _ = a
+
+mergeType :: PortType -> PortType -> PortType
+mergeType Reg Wire = Reg
+mergeType Wire Reg = Reg
+mergeType a _ = a
+
+mergePorts :: Port -> Port -> Port
+mergePorts (Port t1 s1 r1 n1) (Port t2 s2 r2 n2) =
+  Port (mergeType t1 t2) (s1 || s2) (if r1 == 0 then r2 else r1) n1
+
+mergeIO :: ModItem a -> ModItem a -> ModItem a
+mergeIO (Decl a1 b1 c1) (Decl a2 b2 c2) = Decl (mergeMaybe a1 a2) (mergePorts b1 b2) (mergeMaybe c1 c2)
+mergeIO a _ = a
+
+genmoditem :: Map.Map Identifier (ModItem a) -> ModItem a -> Map.Map Identifier (ModItem a)
+genmoditem m (Decl a b c) =
+  Map.insertWith mergeIO (b^.portName) (Decl a b c) m
+genmoditem m b = m
+
+modifyelements :: [ModItem a] -> [ModItem a]
+modifyelements ma = ndecl <> nodecl
+  where
+    ndecl = Map.elems $ foldl genmoditem Map.empty ma
+    isDecl Decl{} = True
+    isDecl _ = False
+    nodecl = filter isDecl ma
+
 -- | Parses a 'String' into 'Verilog' by skipping any beginning whitespace
 -- and then parsing multiple Verilog source.
 parseVerilogSrc :: Parser (Verilog ann)
@@ -537,7 +569,7 @@ parseVerilog ::
   -- message if parse fails.
   Either Text (Verilog ann)
 parseVerilog s =
-  bimap showT id
+  bimap showT id --(_Wrapped.traverse.modItems %~ modifyelements)
     . parse parseVerilogSrc (T.unpack s)
     . alexScanTokens
     . preprocess [] (T.unpack s)
-- 
cgit