From 0636119cb5faf8e55a4a17bb00d15d6710679c35 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Tue, 22 Jan 2019 19:01:44 +0000
Subject: Better multithreading

---
 src/VeriFuzz/Simulator/General.hs | 4 ++++
 src/VeriFuzz/Simulator/Icarus.hs  | 2 +-
 src/VeriFuzz/Simulator/Xst.hs     | 8 ++++----
 src/VeriFuzz/Simulator/Yosys.hs   | 6 +++---
 4 files changed, 12 insertions(+), 8 deletions(-)

(limited to 'src')

diff --git a/src/VeriFuzz/Simulator/General.hs b/src/VeriFuzz/Simulator/General.hs
index 538ecaa..543c139 100644
--- a/src/VeriFuzz/Simulator/General.hs
+++ b/src/VeriFuzz/Simulator/General.hs
@@ -55,3 +55,7 @@ timeout_ = command1_ "timeout" ["180"] . toTextIgnore
 bsToI :: ByteString -> Integer
 bsToI = B.foldl' (\i b -> (i `shiftL` 8) + fromIntegral b) 0
 {-# INLINE bsToI #-}
+
+noPrint :: Sh a -> Sh a
+noPrint =
+  print_stdout False . print_stderr False
diff --git a/src/VeriFuzz/Simulator/Icarus.hs b/src/VeriFuzz/Simulator/Icarus.hs
index 4782585..3518447 100644
--- a/src/VeriFuzz/Simulator/Icarus.hs
+++ b/src/VeriFuzz/Simulator/Icarus.hs
@@ -58,5 +58,5 @@ runSimIcarus sim m bss = do
   let newtb     = instantiateMod m tb
   let modWithTb = VerilogSrc $ Description <$> [newtb, m]
   writefile "main.v" $ genSource modWithTb
-  run_ (icarusPath sim) ["-o", "main", "main.v"]
+  noPrint $ run_ (icarusPath sim) ["-o", "main", "main.v"]
   hash <$> run (vvpPath sim) ["main"]
diff --git a/src/VeriFuzz/Simulator/Xst.hs b/src/VeriFuzz/Simulator/Xst.hs
index 415a45e..03c1707 100644
--- a/src/VeriFuzz/Simulator/Xst.hs
+++ b/src/VeriFuzz/Simulator/Xst.hs
@@ -42,10 +42,10 @@ runSynthXst sim m outf = do
   writefile xstFile $ xstSynthConfig m
   writefile prjFile [st|verilog work "rtl.v"|]
   writefile "rtl.v" $ genSource m
-  timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile]
-  run_ (netgenPath sim)
-       ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf]
-  run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf]
+  noPrint $ timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile]
+  noPrint $ run_ (netgenPath sim)
+    ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf]
+  noPrint $ run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf]
  where
   modFile = fromText $ modName m
   xstFile = modFile <.> "xst"
diff --git a/src/VeriFuzz/Simulator/Yosys.hs b/src/VeriFuzz/Simulator/Yosys.hs
index 286a132..c63d549 100644
--- a/src/VeriFuzz/Simulator/Yosys.hs
+++ b/src/VeriFuzz/Simulator/Yosys.hs
@@ -47,7 +47,7 @@ writeSimFile _ m file = do
 runSynthYosys :: Yosys -> ModDecl -> FilePath -> Sh ()
 runSynthYosys sim m outf = do
   writefile inpf $ genSource m
-  run_ (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp]
+  noPrint $ run_ (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp]
  where
   inpf = "rtl.v"
   inp  = toTextIgnore inpf
@@ -64,7 +64,7 @@ runEquivYosys yosys sim1 sim2 m = do
   writefile checkFile $ yosysSatConfig sim1 sim2 m
   runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|]
   runMaybeSynth sim2 m
-  run_ (yosysPath yosys) [toTextIgnore checkFile]
+  noPrint $ run_ (yosysPath yosys) [toTextIgnore checkFile]
   where
     checkFile = fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|]
 
@@ -75,4 +75,4 @@ runEquiv yosys sim1 sim2 m = do
   writefile "test.sby" $ sbyConfig root sim1 sim2 m
   runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|]
   runMaybeSynth sim2 m
-  run_ "sby" ["test.sby"]
+  noPrint $ run_ "sby" ["test.sby"]
-- 
cgit