From 0afc44989b841fcb99e0af1d1bff79f82e700313 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 3 Apr 2019 19:54:25 +0100 Subject: Add verilog modules to equivalence checking --- src/VeriFuzz/Sim/Template.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs index bd58b83..0fc74a0 100644 --- a/src/VeriFuzz/Sim/Template.hs +++ b/src/VeriFuzz/Sim/Template.hs @@ -110,7 +110,7 @@ top.v |] where mis = src ^.. getSourceId - deps = ["cells_cmos.v", "cells_cyclone_v.v", "cells_verific.v", "cells_xilinx_7.v"] + deps = ["cells_cmos.v", "cells_cyclone_v.v", "cells_verific.v", "cells_xilinx_7.v", "cells_yosys.v"] depList = T.intercalate "\n" $ toTextIgnore -- cgit