From 109f8ad0b542ba94839796a4a01e250ed88027b5 Mon Sep 17 00:00:00 2001
From: Yann Herklotz Grave <git@yannherklotzgrave.com>
Date: Fri, 1 Mar 2019 19:22:04 +0000
Subject: Some formatting

---
 src/VeriFuzz/Reduce.hs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs
index 2a1b8b4..17e7e8e 100644
--- a/src/VeriFuzz/Reduce.hs
+++ b/src/VeriFuzz/Reduce.hs
@@ -116,7 +116,8 @@ reduce_
 reduce_ repl eval src = do
     replAnswer <- sequenceA $ evalIfNotEmpty <$> replacement
     case (replacement, replAnswer) of
-        (Single s, Single False    ) -> if s /= src then reduce eval s else return s
+        (Single s, Single False) ->
+            if s /= src then reduce eval s else return s
         (Dual _ l, Dual True False ) -> reduce eval l
         (Dual r _, Dual False True ) -> reduce eval r
         (Dual r l, Dual False False) -> do
@@ -126,7 +127,7 @@ reduce_ repl eval src = do
                 then return lreduced
                 else return rreduced
         (None, None) -> return src
-        _ -> return src
+        _            -> return src
   where
     replacement = repl src
     evalIfNotEmpty m = do
@@ -144,5 +145,4 @@ reduce
     :: (SourceInfo -> IO Bool) -- ^ Failed or not.
     -> SourceInfo              -- ^ Input verilog source to be reduced.
     -> IO SourceInfo           -- ^ Reduced output.
-reduce eval src = reduce_ halveAssigns eval src
-                  >>= reduce_ halveExpr eval
+reduce eval src = reduce_ halveAssigns eval src >>= reduce_ halveExpr eval
-- 
cgit