From 14b900abdcd96ad540e7ea0c086cd78bb96ccc4a Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 30 Nov 2018 23:34:41 +0000 Subject: Add assignment to ModuleItem --- src/Test/VeriFuzz/VerilogAST.hs | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/Test/VeriFuzz/VerilogAST.hs b/src/Test/VeriFuzz/VerilogAST.hs index d4514cc..8314acb 100644 --- a/src/Test/VeriFuzz/VerilogAST.hs +++ b/src/Test/VeriFuzz/VerilogAST.hs @@ -65,7 +65,7 @@ data Port = Port { _portName :: Identifier } deriving (Show) makeLenses ''Port -newtype ModuleItem = ModuleItem { _getModuleItem :: Text } +data ModuleItem = Assign ContAssign deriving (Show) makeLenses ''ModuleItem @@ -81,6 +81,5 @@ newtype Description = Description { _getDescription :: ModuleDecl } makeLenses ''Description newtype SourceText = SourceText { _getSourceText :: [Description] } - deriving (Show - ) + deriving (Show) makeLenses ''SourceText -- cgit