From 2b461deaf32e065a71d83235f3c5648eea93fb19 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Fri, 25 Oct 2019 09:05:31 +0100
Subject: Fix subtle issue with module generation

---
 src/Verismith/Generate.hs | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/Verismith/Generate.hs b/src/Verismith/Generate.hs
index a896c3e..25b9306 100644
--- a/src/Verismith/Generate.hs
+++ b/src/Verismith/Generate.hs
@@ -445,6 +445,7 @@ instantiate (ModDecl i outP inP _ _) = do
     context <- lget
     outs    <- replicateM (length outP) (nextPort Wire)
     ins <- take (length inpFixed) <$> Hog.shuffle (context ^. variables)
+    insLit <- replicateM (length inpFixed - length ins) (Number <$> genBitVec)
     mapM_ (uncurry process) . zip (ins ^.. traverse . portName) $ inpFixed ^.. traverse . portSize
     ident <- makeIdentifier "modinst"
     vs <- view variables <$> lget
-- 
cgit