From 451746e7916914d7b1731ef2f4dfd966557bd0f9 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 29 Nov 2018 18:54:18 +0000 Subject: Add Verilog AST --- src/Test/VeriFuzz/VerilogAST.hs | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 src/Test/VeriFuzz/VerilogAST.hs (limited to 'src') diff --git a/src/Test/VeriFuzz/VerilogAST.hs b/src/Test/VeriFuzz/VerilogAST.hs new file mode 100644 index 0000000..897855b --- /dev/null +++ b/src/Test/VeriFuzz/VerilogAST.hs @@ -0,0 +1,13 @@ +module Test.VeriFuzz.VerilogAST where + +data ModuleItem = + +-- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module' +data ModuleDecl = ModuleDecl { moduleId :: Text + , ports :: [Port] + , moduleItem :: ModuleItem + } + +type Description = ModuleDecl + +type SourceText = [Description] -- cgit