From 49291d38214cbdbf084fecc931e7e5d5732a742c Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Wed, 23 Jan 2019 19:36:18 +0000
Subject: Add echo do all the simulators

---
 src/VeriFuzz/Simulator/Icarus.hs | 1 +
 src/VeriFuzz/Simulator/Xst.hs    | 5 +++++
 src/VeriFuzz/Simulator/Yosys.hs  | 3 +++
 3 files changed, 9 insertions(+)

(limited to 'src')

diff --git a/src/VeriFuzz/Simulator/Icarus.hs b/src/VeriFuzz/Simulator/Icarus.hs
index 3518447..527322a 100644
--- a/src/VeriFuzz/Simulator/Icarus.hs
+++ b/src/VeriFuzz/Simulator/Icarus.hs
@@ -58,5 +58,6 @@ runSimIcarus sim m bss = do
   let newtb     = instantiateMod m tb
   let modWithTb = VerilogSrc $ Description <$> [newtb, m]
   writefile "main.v" $ genSource modWithTb
+  echoP "Run icarus"
   noPrint $ run_ (icarusPath sim) ["-o", "main", "main.v"]
   hash <$> run (vvpPath sim) ["main"]
diff --git a/src/VeriFuzz/Simulator/Xst.hs b/src/VeriFuzz/Simulator/Xst.hs
index 03c1707..52272c3 100644
--- a/src/VeriFuzz/Simulator/Xst.hs
+++ b/src/VeriFuzz/Simulator/Xst.hs
@@ -15,8 +15,10 @@ Xst (ise) simulator implementation.
 module VeriFuzz.Simulator.Xst where
 
 import           Control.Lens                         hiding ((<.>))
+import qualified Data.Text                            as T
 import           Prelude                              hiding (FilePath)
 import           Shelly
+import           System.FilePath.Posix                (takeBaseName)
 import           Text.Shakespeare.Text                (st)
 import           VeriFuzz.Simulator.General
 import           VeriFuzz.Simulator.Internal.Template
@@ -42,9 +44,12 @@ runSynthXst sim m outf = do
   writefile xstFile $ xstSynthConfig m
   writefile prjFile [st|verilog work "rtl.v"|]
   writefile "rtl.v" $ genSource m
+  echoP "Run xst"
   noPrint $ timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile]
+  echoP "Run netgen"
   noPrint $ run_ (netgenPath sim)
     ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf]
+  echoP "Clean synthesized file"
   noPrint $ run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf]
  where
   modFile = fromText $ modName m
diff --git a/src/VeriFuzz/Simulator/Yosys.hs b/src/VeriFuzz/Simulator/Yosys.hs
index c63d549..e18de5a 100644
--- a/src/VeriFuzz/Simulator/Yosys.hs
+++ b/src/VeriFuzz/Simulator/Yosys.hs
@@ -47,6 +47,7 @@ writeSimFile _ m file = do
 runSynthYosys :: Yosys -> ModDecl -> FilePath -> Sh ()
 runSynthYosys sim m outf = do
   writefile inpf $ genSource m
+  echoP "Run yosim"
   noPrint $ run_ (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp]
  where
   inpf = "rtl.v"
@@ -64,6 +65,7 @@ runEquivYosys yosys sim1 sim2 m = do
   writefile checkFile $ yosysSatConfig sim1 sim2 m
   runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|]
   runMaybeSynth sim2 m
+  echoP "Run yosys"
   noPrint $ run_ (yosysPath yosys) [toTextIgnore checkFile]
   where
     checkFile = fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|]
@@ -75,4 +77,5 @@ runEquiv yosys sim1 sim2 m = do
   writefile "test.sby" $ sbyConfig root sim1 sim2 m
   runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|]
   runMaybeSynth sim2 m
+  echoP "Run SymbiYosys"
   noPrint $ run_ "sby" ["test.sby"]
-- 
cgit