From 4f9e123fc9b00986f627aeaf0eee6c29be1b3780 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 31 Dec 2018 19:20:54 +0100 Subject: Fix build errors --- src/Test/VeriFuzz/Graph/CodeGen.hs | 6 ++++-- src/Test/VeriFuzz/Verilog/CodeGen.hs | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/Test/VeriFuzz/Graph/CodeGen.hs b/src/Test/VeriFuzz/Graph/CodeGen.hs index 5d3232c..b890a04 100644 --- a/src/Test/VeriFuzz/Graph/CodeGen.hs +++ b/src/Test/VeriFuzz/Graph/CodeGen.hs @@ -14,10 +14,12 @@ module Test.VeriFuzz.Graph.CodeGen ( generate ) where +import Data.Foldable (fold) import Data.Graph.Inductive (Graph, LNode, Node, indeg, labNodes, nodes, outdeg, pre) import Data.Maybe (fromMaybe) -import Data.Text (Text, empty, pack) +import Data.Text (Text) +import qualified Data.Text as T import Test.VeriFuzz.Circuit import Test.VeriFuzz.Internal.Gen import Test.VeriFuzz.Internal.Shared @@ -37,7 +39,7 @@ lastEl n = fromNode <$> safe head n toStmnt :: (Graph gr) => gr Gate e -> LNode Gate -> Text toStmnt graph (n, g) = - fromMaybe empty $ Just " assign " <> Just (fromNode n) + fromMaybe T.empty $ Just " assign " <> Just (fromNode n) <> Just " = " <> statList g nodeL <> lastEl nodeL <> Just ";\n" where nodeL = pre graph n diff --git a/src/Test/VeriFuzz/Verilog/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs index 4fecaec..d0b1fec 100644 --- a/src/Test/VeriFuzz/Verilog/CodeGen.hs +++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs @@ -14,6 +14,7 @@ This module generates the code from the Verilog AST defined in module Test.VeriFuzz.Verilog.CodeGen where import Control.Lens +import Data.Foldable (fold) import Data.Maybe (fromMaybe, isNothing) import Data.Text (Text) import qualified Data.Text as T -- cgit