From 50f0039fb733cef73a749c098b63fff202641ea1 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 31 Dec 2018 19:39:57 +0100 Subject: Add missing case in function --- src/Test/VeriFuzz/Verilog/CodeGen.hs | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/Test/VeriFuzz/Verilog/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs index 3c1f958..11b9743 100644 --- a/src/Test/VeriFuzz/Verilog/CodeGen.hs +++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs @@ -165,6 +165,8 @@ genLVal (RegExpr id expr) = id ^. getIdentifier <> " [" <> genExpr expr <> "]" genLVal (RegSize id msb lsb) = id ^. getIdentifier <> " [" <> genConstExpr msb <> ":" <> genConstExpr lsb <> "]" +genLVal (RegConcat e) = + "{" <> comma (genExpr <$> e) <> "}" genConstExpr :: ConstExpr -> Text genConstExpr (ConstExpr num) = showT num -- cgit