From 5e3abd02be92f801a86d17501d82b22c644946b7 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 1 Jan 2019 15:35:04 +0100 Subject: Remove Monoid instance for LVal, as it does not quite fit --- src/Test/VeriFuzz/Verilog/AST.hs | 9 --------- 1 file changed, 9 deletions(-) (limited to 'src') diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs index b643db5..4f2c52d 100644 --- a/src/Test/VeriFuzz/Verilog/AST.hs +++ b/src/Test/VeriFuzz/Verilog/AST.hs @@ -71,15 +71,6 @@ data LVal = RegId Identifier | RegConcat { _regConc :: [Expr] } deriving (Eq) -instance Semigroup LVal where - (RegConcat a) <> (RegConcat b) = RegConcat $ a <> b - (RegConcat a) <> b = RegConcat $ a <> [b] - a <> (RegConcat b) = RegConcat $ a : b - a <> b = RegConcat [a, b] - -instance Monoid LVal where - mempty = RegConcat [] - -- | Binary operators that are currently supported in the verilog generation. data BinaryOperator = BinPlus -- ^ @+@ | BinMinus -- ^ @-@ -- cgit