From 6610c9a341c568ea369049a7a3d33b64ab4f2815 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 31 Dec 2018 19:36:23 +0100 Subject: Add show instance and add concat to reglval --- src/Test/VeriFuzz/Verilog/AST.hs | 59 +++++++++++++++--------------- src/Test/VeriFuzz/Verilog/Arbitrary.hs | 2 +- src/Test/VeriFuzz/Verilog/CodeGen.hs | 65 ++++++++++++++++++++++++++++------ src/Test/VeriFuzz/Verilog/Mutate.hs | 4 +-- 4 files changed, 88 insertions(+), 42 deletions(-) (limited to 'src') diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs index 5ae3202..83616dc 100644 --- a/src/Test/VeriFuzz/Verilog/AST.hs +++ b/src/Test/VeriFuzz/Verilog/AST.hs @@ -30,7 +30,7 @@ class Source a where -- be lowercase and uppercase for now. This might change in the future though, -- as Verilog supports many more characters in Identifiers. newtype Identifier = Identifier { _getIdentifier :: Text } - deriving (Show, Eq, Ord) + deriving (Eq) instance IsString Identifier where fromString = Identifier . T.pack @@ -42,22 +42,23 @@ instance Monoid Identifier where mempty = Identifier mempty newtype Delay = Delay { _delay :: Int } - deriving (Show, Eq, Ord) + deriving (Eq) data Event = EId Identifier | EExpr Expr | EAll - deriving (Show, Eq, Ord) + deriving (Eq) -data RegLVal = RegId Identifier - | RegExpr { _regExprId :: Identifier - , _regExpr :: Expr - } - | RegSize { _regSizeId :: Identifier - , _regSizeMSB :: ConstExpr - , _regSizeLSB :: ConstExpr - } - deriving (Show, Eq, Ord) +data LVal = RegId Identifier + | RegExpr { _regExprId :: Identifier + , _regExpr :: Expr + } + | RegSize { _regSizeId :: Identifier + , _regSizeMSB :: ConstExpr + , _regSizeLSB :: ConstExpr + } + | RegConcat { _regConc :: [Expr] } + deriving (Eq) -- | Binary operators that are currently supported in the verilog generation. data BinaryOperator = BinPlus -- ^ @+@ @@ -85,7 +86,7 @@ data BinaryOperator = BinPlus -- ^ @+@ | BinLSR -- ^ @>>@ | BinASL -- ^ @<<<@ | BinASR -- ^ @>>>@ - deriving (Show, Eq, Ord) + deriving (Eq) -- | Unary operators that are currently supported by the generator. data UnaryOperator = UnPlus -- ^ @+@ @@ -98,7 +99,7 @@ data UnaryOperator = UnPlus -- ^ @+@ | UnXor -- ^ @^@ | UnNxor -- ^ @~^@ | UnNxorInv -- ^ @^~@ - deriving (Show, Eq, Ord) + deriving (Eq) -- | Verilog expression, which can either be a primary expression, unary -- expression, binary operator expression or a conditional expression. @@ -119,7 +120,7 @@ data Expr = Number { _numSize :: Int , _exprFalse :: Expr } | Str { _exprStr :: Text } - deriving (Show, Eq, Ord) + deriving (Eq) instance Num Expr where a + b = BinOp a BinPlus b @@ -138,7 +139,7 @@ instance Monoid Expr where mconcat = Concat newtype ConstExpr = ConstExpr { _constNum :: Int } - deriving (Show, Eq, Ord) + deriving (Eq) instance Num ConstExpr where ConstExpr a + ConstExpr b = ConstExpr $ a + b @@ -152,29 +153,29 @@ instance Num ConstExpr where data PortDir = PortIn -- ^ Input direction for port (@input@). | PortOut -- ^ Output direction for port (@output@). | PortInOut -- ^ Inout direction for port (@inout@). - deriving (Show, Eq, Ord) + deriving (Eq) data PortType = Wire | Reg { _regSigned :: Bool } - deriving (Show, Eq, Ord) + deriving (Eq) -- | Port declaration. data Port = Port { _portType :: PortType , _portSize :: Int , _portName :: Identifier - } deriving (Show, Eq, Ord) + } deriving (Eq) newtype ModConn = ModConn { _modConn :: Expr } - deriving (Show, Eq, Ord) + deriving (Eq) -data Assign = Assign { _assignReg :: RegLVal +data Assign = Assign { _assignReg :: LVal , _assignDelay :: Maybe Delay , _assignExpr :: Expr - } deriving (Show, Eq, Ord) + } deriving (Eq) data ContAssign = ContAssign { _contAssignNetLVal :: Identifier , _contAssignExpr :: Expr - } deriving (Show, Eq, Ord) + } deriving (Eq) -- | Stmnts in Verilog. data Stmnt = TimeCtrl { _statDelay :: Delay @@ -190,7 +191,7 @@ data Stmnt = TimeCtrl { _statDelay :: Delay | TaskEnable Task | SysTaskEnable Task | EmptyStat - deriving (Show, Eq, Ord) + deriving (Eq) instance Semigroup Stmnt where a <> b = mconcat [a, b] @@ -201,7 +202,7 @@ instance Monoid Stmnt where data Task = Task { _taskName :: Identifier , _taskExpr :: [Expr] - } deriving (Show, Eq, Ord) + } deriving (Eq) -- | Module item which is the body of the module expression. data ModItem = ModCA ContAssign @@ -214,22 +215,22 @@ data ModItem = ModCA ContAssign | Decl { declDir :: Maybe PortDir , declPort :: Port } - deriving (Show, Eq, Ord) + deriving (Eq) -- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module' data ModDecl = ModDecl { _moduleId :: Identifier , _modOutPorts :: [Port] , _modInPorts :: [Port] , _moduleItems :: [ModItem] - } deriving (Show, Eq, Ord) + } deriving (Eq) -- | Description of the Verilog module. newtype Description = Description { _getDescription :: ModDecl } - deriving (Show, Eq, Ord) + deriving (Eq) -- | The complete sourcetext for the Verilog module. newtype VerilogSrc = VerilogSrc { _getVerilogSrc :: [Description] } - deriving (Show, Eq, Ord) + deriving (Eq) instance Semigroup VerilogSrc where VerilogSrc a <> VerilogSrc b = VerilogSrc $ a ++ b diff --git a/src/Test/VeriFuzz/Verilog/Arbitrary.hs b/src/Test/VeriFuzz/Verilog/Arbitrary.hs index 5f30b73..1bcb727 100644 --- a/src/Test/VeriFuzz/Verilog/Arbitrary.hs +++ b/src/Test/VeriFuzz/Verilog/Arbitrary.hs @@ -144,7 +144,7 @@ instance QC.Arbitrary ModConn where instance QC.Arbitrary ConstExpr where arbitrary = ConstExpr <$> positiveArb -instance QC.Arbitrary RegLVal where +instance QC.Arbitrary LVal where arbitrary = QC.oneof [ RegId <$> QC.arbitrary , RegExpr <$> QC.arbitrary <*> QC.arbitrary , RegSize <$> QC.arbitrary <*> QC.arbitrary <*> QC.arbitrary diff --git a/src/Test/VeriFuzz/Verilog/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs index d0b1fec..3c1f958 100644 --- a/src/Test/VeriFuzz/Verilog/CodeGen.hs +++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs @@ -159,11 +159,11 @@ genEvent EAll = "@*" genDelay :: Delay -> Text genDelay (Delay i) = "#" <> showT i -genRegLVal :: RegLVal -> Text -genRegLVal (RegId id) = id ^. getIdentifier -genRegLVal (RegExpr id expr) = +genLVal :: LVal -> Text +genLVal (RegId id) = id ^. getIdentifier +genLVal (RegExpr id expr) = id ^. getIdentifier <> " [" <> genExpr expr <> "]" -genRegLVal (RegSize id msb lsb) = +genLVal (RegSize id msb lsb) = id ^. getIdentifier <> " [" <> genConstExpr msb <> ":" <> genConstExpr lsb <> "]" genConstExpr :: ConstExpr -> Text @@ -177,7 +177,7 @@ genPortType (Reg signed) genAssign :: Text -> Assign -> Text genAssign op (Assign r d e) = - genRegLVal r <> op <> fromMaybe "" (genDelay <$> d) <> genExpr e + genLVal r <> op <> fromMaybe "" (genDelay <$> d) <> genExpr e genStmnt :: Stmnt -> Text genStmnt (TimeCtrl d stat) = genDelay d <> " " <> defMap stat @@ -215,8 +215,8 @@ instance Source PortType where instance Source ConstExpr where genSource = genConstExpr -instance Source RegLVal where - genSource = genRegLVal +instance Source LVal where + genSource = genLVal instance Source Delay where genSource = genDelay @@ -251,7 +251,52 @@ instance Source Description where instance Source VerilogSrc where genSource = genVerilogSrc -newtype SourceShowable a = SrcShow { unSrcShow :: a } +-- Show instances -instance (Source a) => Show (SourceShowable a) where - show s = T.unpack $ genSource (unSrcShow s) +instance Show Task where + show = T.unpack . genTask + +instance Show Stmnt where + show = T.unpack . genStmnt + +instance Show PortType where + show = T.unpack . genPortType + +instance Show ConstExpr where + show = T.unpack . genConstExpr + +instance Show LVal where + show = T.unpack . genLVal + +instance Show Delay where + show = T.unpack . genDelay + +instance Show Event where + show = T.unpack . genEvent + +instance Show UnaryOperator where + show = T.unpack . genUnaryOperator + +instance Show Expr where + show = T.unpack . genExpr + +instance Show ContAssign where + show = T.unpack . genContAssign + +instance Show ModItem where + show = T.unpack . genModuleItem + +instance Show PortDir where + show = T.unpack . genPortDir + +instance Show Port where + show = T.unpack . genPort + +instance Show ModDecl where + show = T.unpack . genModuleDecl + +instance Show Description where + show = T.unpack . genDescription + +instance Show VerilogSrc where + show = T.unpack . genVerilogSrc diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs index 9175664..b22fc2c 100644 --- a/src/Test/VeriFuzz/Verilog/Mutate.hs +++ b/src/Test/VeriFuzz/Verilog/Mutate.hs @@ -84,7 +84,7 @@ nestUpTo i src = -- it to the body of the second module. It first has to make all the inputs into -- @reg@. -- --- >>> SrcShow $ instantiateMod mod main +-- >>> instantiateMod mod main -- module main; -- wire [4:0] y; -- reg [4:0] x; @@ -104,7 +104,7 @@ instantiateMod mod main = -- | Initialise all the inputs and outputs to a module. -- --- >>> SrcShow $ initMod mod +-- >>> initMod mod -- module m(y, x); -- output wire [4:0] y; -- input wire [4:0] x; -- cgit