From 686bc953c50cf23b96dba4f182e8005289e71b98 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sat, 2 Feb 2019 13:44:24 +0000
Subject: Add mutation for declaration

---
 src/VeriFuzz/Mutate.hs | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src')

diff --git a/src/VeriFuzz/Mutate.hs b/src/VeriFuzz/Mutate.hs
index 705e607..7295b63 100644
--- a/src/VeriFuzz/Mutate.hs
+++ b/src/VeriFuzz/Mutate.hs
@@ -166,3 +166,8 @@ makeTopAssert = (modItems %~ (++ [assert])) . (modInPorts %~ addClk) . makeTop 2
     [TaskEnable $ Task "assert" [BinOp (Id "y_1") BinEq (Id "y_2")]]
   e = EPosEdge "clk"
   addClk = ((Port Wire 1 "clk") :)
+
+declareMod :: [Port] -> ModDecl -> ModDecl
+declareMod ports = modItems %~ (decl++)
+  where
+    decl = Decl Nothing <$> ports
-- 
cgit