From 7239f17dafcd5eb2c742cdd20e88a7256d977108 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Fri, 8 Feb 2019 15:49:36 +0000
Subject: Remove _ModCA and replace it by modContAssign

---
 src/VeriFuzz/ASTGen.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/VeriFuzz/ASTGen.hs b/src/VeriFuzz/ASTGen.hs
index 5d4d8bc..d113bbb 100644
--- a/src/VeriFuzz/ASTGen.hs
+++ b/src/VeriFuzz/ASTGen.hs
@@ -75,7 +75,7 @@ genModuleDeclAST c = ModDecl i output ports items
   output = [Port Wire 90 "y"]
   a = genAssignAST c
   items  = a ++ [ModCA . ContAssign "y" . fold $ Id <$> assigns]
-  assigns = a ^.. traverse . _ModCA . contAssignNetLVal
+  assigns = a ^.. traverse . modContAssign . contAssignNetLVal
 
 generateAST :: Circuit -> VerilogSrc
 generateAST c = VerilogSrc [Description $ genModuleDeclAST c]
-- 
cgit