From 75e6abdcb78c70b7449e5fd7f48d8a3e6b3d164b Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sat, 19 Jan 2019 19:35:30 +0000 Subject: Set column to 100 --- src/VeriFuzz/Graph/ASTGen.hs | 3 +-- src/VeriFuzz/Graph/CodeGen.hs | 3 +-- src/VeriFuzz/Graph/Random.hs | 3 +-- src/VeriFuzz/Internal/Gen.hs | 8 +------ src/VeriFuzz/Simulator/Icarus.hs | 8 ++----- src/VeriFuzz/Simulator/Xst.hs | 4 ++-- src/VeriFuzz/Verilog/CodeGen.hs | 48 +++++++++++++--------------------------- src/VeriFuzz/Verilog/Helpers.hs | 4 +--- src/VeriFuzz/Verilog/Mutate.hs | 33 ++++++--------------------- 9 files changed, 31 insertions(+), 83 deletions(-) (limited to 'src') diff --git a/src/VeriFuzz/Graph/ASTGen.hs b/src/VeriFuzz/Graph/ASTGen.hs index 0403f51..ad7dd50 100644 --- a/src/VeriFuzz/Graph/ASTGen.hs +++ b/src/VeriFuzz/Graph/ASTGen.hs @@ -75,8 +75,7 @@ genModuleDeclAST c = ModDecl i output ports items i = Identifier "gen_module" ports = genPortsAST inputsC c output = [Port Wire 90 "y"] - items = - genAssignAST c ++ [ModCA . ContAssign "y" . fold $ portToExpr <$> ports] + items = genAssignAST c ++ [ModCA . ContAssign "y" . fold $ portToExpr <$> ports] generateAST :: Circuit -> VerilogSrc generateAST c = VerilogSrc [Description $ genModuleDeclAST c] diff --git a/src/VeriFuzz/Graph/CodeGen.hs b/src/VeriFuzz/Graph/CodeGen.hs index 3c45a9c..56b28aa 100644 --- a/src/VeriFuzz/Graph/CodeGen.hs +++ b/src/VeriFuzz/Graph/CodeGen.hs @@ -35,8 +35,7 @@ toOperator Or = " | " toOperator Xor = " ^ " statList :: Gate -> [Node] -> Maybe Text -statList g n = toStr <$> safe tail n - where toStr = fold . fmap ((<> toOperator g) . fromNode) +statList g n = toStr <$> safe tail n where toStr = fold . fmap ((<> toOperator g) . fromNode) lastEl :: [Node] -> Maybe Text lastEl n = fromNode <$> safe head n diff --git a/src/VeriFuzz/Graph/Random.hs b/src/VeriFuzz/Graph/Random.hs index 5b36c48..573c179 100644 --- a/src/VeriFuzz/Graph/Random.hs +++ b/src/VeriFuzz/Graph/Random.hs @@ -25,8 +25,7 @@ import Test.QuickCheck ( Arbitrary import qualified Test.QuickCheck as QC dupFolder :: (Eq a, Eq b) => Context a b -> [Context a b] -> [Context a b] -dupFolder cont ns = unique cont : ns - where unique (a, b, c, d) = (nub a, b, c, nub d) +dupFolder cont ns = unique cont : ns where unique (a, b, c, d) = (nub a, b, c, nub d) -- | Remove duplicates. rDups :: (Eq a, Eq b) => Gr a b -> Gr a b diff --git a/src/VeriFuzz/Internal/Gen.hs b/src/VeriFuzz/Internal/Gen.hs index 6e44524..d821cd7 100644 --- a/src/VeriFuzz/Internal/Gen.hs +++ b/src/VeriFuzz/Internal/Gen.hs @@ -24,13 +24,7 @@ fromNode node = T.pack $ "w" <> show node filterGr :: (Graph gr) => gr n e -> (Node -> Bool) -> [Node] filterGr graph f = filter f $ G.nodes graph -only - :: (Graph gr) - => gr n e - -> (gr n e -> Node -> Int) - -> (gr n e -> Node -> Int) - -> Node - -> Bool +only :: (Graph gr) => gr n e -> (gr n e -> Node -> Int) -> (gr n e -> Node -> Int) -> Node -> Bool only graph fun1 fun2 n = fun1 graph n == 0 && fun2 graph n /= 0 inputs :: (Graph gr) => gr n e -> [Node] diff --git a/src/VeriFuzz/Simulator/Icarus.hs b/src/VeriFuzz/Simulator/Icarus.hs index 443f096..fdb1ad6 100644 --- a/src/VeriFuzz/Simulator/Icarus.hs +++ b/src/VeriFuzz/Simulator/Icarus.hs @@ -38,15 +38,11 @@ defaultIcarus = Icarus "iverilog" "vvp" addDisplay :: [Stmnt] -> [Stmnt] addDisplay s = concat $ transpose - [ s - , replicate l $ TimeCtrl 1 Nothing - , replicate l . SysTaskEnable $ Task "display" ["%h", Id "y"] - ] + [s, replicate l $ TimeCtrl 1 Nothing, replicate l . SysTaskEnable $ Task "display" ["%h", Id "y"]] where l = length s assignFunc :: [Port] -> ByteString -> Stmnt -assignFunc inp bs = - NonBlockAssign . Assign conc Nothing . Number (B.length bs * 4) $ bsToI bs +assignFunc inp bs = NonBlockAssign . Assign conc Nothing . Number (B.length bs * 4) $ bsToI bs where conc = RegConcat (portToExpr <$> inp) runSimIcarus :: Icarus -> ModDecl -> [ByteString] -> Sh Int diff --git a/src/VeriFuzz/Simulator/Xst.hs b/src/VeriFuzz/Simulator/Xst.hs index 3209caf..1a0763c 100644 --- a/src/VeriFuzz/Simulator/Xst.hs +++ b/src/VeriFuzz/Simulator/Xst.hs @@ -33,8 +33,8 @@ instance Synthesize Xst where runSynth = runSynthXst defaultXst :: Xst -defaultXst = Xst "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xst" - "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/netgen" +defaultXst = + Xst "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xst" "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/netgen" -- brittany-disable-next-binding runSynthXst :: Xst -> ModDecl -> FilePath -> Sh () diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index 338838f..34194a6 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -55,14 +55,7 @@ genDescription desc = genModuleDecl $ desc ^. getDescription -- | Generate the 'ModDecl' for a module and convert it to 'Text'. genModuleDecl :: ModDecl -> Text genModuleDecl m = - "module " - <> m - ^. moduleId - . getIdentifier - <> ports - <> ";\n" - <> modI - <> "endmodule\n" + "module " <> m ^. moduleId . getIdentifier <> ports <> ";\n" <> modI <> "endmodule\n" where ports | noIn && noOut = "" | otherwise = "(" <> comma (genModPort <$> outIn) <> ")" @@ -96,10 +89,9 @@ genModuleItem :: ModItem -> Text genModuleItem (ModCA ca) = genContAssign ca genModuleItem (ModInst (Identifier i) (Identifier name) conn) = i <> " " <> name <> "(" <> comma (genExpr . _modConn <$> conn) <> ")" <> ";\n" -genModuleItem (Initial stat) = "initial " <> genStmnt stat -genModuleItem (Always stat) = "always " <> genStmnt stat -genModuleItem (Decl dir port) = - (maybe "" makePort dir) <> genPort port <> ";\n" +genModuleItem (Initial stat ) = "initial " <> genStmnt stat +genModuleItem (Always stat ) = "always " <> genStmnt stat +genModuleItem (Decl dir port) = (maybe "" makePort dir) <> genPort port <> ";\n" where makePort = (<> " ") . genPortDir -- | Generate continuous assignment @@ -111,15 +103,13 @@ genContAssign (ContAssign val e) = "assign " <> name <> " = " <> expr <> ";\n" -- | Generate 'Expr' to 'Text'. genExpr :: Expr -> Text -genExpr (BinOp eRhs bin eLhs) = - "(" <> genExpr eRhs <> genBinaryOperator bin <> genExpr eLhs <> ")" -genExpr (Number s n) = showT s <> "'h" <> T.pack (showHex n "") -genExpr (Id i ) = i ^. getIdentifier -genExpr (Concat c ) = "{" <> comma (genExpr <$> c) <> "}" -genExpr (UnOp u e ) = "(" <> genUnaryOperator u <> genExpr e <> ")" -genExpr (Cond l t f) = - "(" <> genExpr l <> " ? " <> genExpr t <> " : " <> genExpr f <> ")" -genExpr (Str t) = "\"" <> t <> "\"" +genExpr (BinOp eRhs bin eLhs) = "(" <> genExpr eRhs <> genBinaryOperator bin <> genExpr eLhs <> ")" +genExpr (Number s n ) = showT s <> "'h" <> T.pack (showHex n "") +genExpr (Id i ) = i ^. getIdentifier +genExpr (Concat c ) = "{" <> comma (genExpr <$> c) <> "}" +genExpr (UnOp u e ) = "(" <> genUnaryOperator u <> genExpr e <> ")" +genExpr (Cond l t f ) = "(" <> genExpr l <> " ? " <> genExpr t <> " : " <> genExpr f <> ")" +genExpr (Str t ) = "\"" <> t <> "\"" -- | Convert 'BinaryOperator' to 'Text'. genBinaryOperator :: BinaryOperator -> Text @@ -177,13 +167,7 @@ genLVal :: LVal -> Text genLVal (RegId i ) = i ^. getIdentifier genLVal (RegExpr i expr) = i ^. getIdentifier <> " [" <> genExpr expr <> "]" genLVal (RegSize i msb lsb) = - i - ^. getIdentifier - <> " [" - <> genConstExpr msb - <> ":" - <> genConstExpr lsb - <> "]" + i ^. getIdentifier <> " [" <> genConstExpr msb <> ":" <> genConstExpr lsb <> "]" genLVal (RegConcat e) = "{" <> comma (genExpr <$> e) <> "}" genConstExpr :: ConstExpr -> Text @@ -195,8 +179,7 @@ genPortType (Reg signed) | signed = "reg signed" | otherwise = "reg" genAssign :: Text -> Assign -> Text -genAssign op (Assign r d e) = - genLVal r <> op <> maybe "" genDelay d <> genExpr e +genAssign op (Assign r d e) = genLVal r <> op <> maybe "" genDelay d <> genExpr e genStmnt :: Stmnt -> Text genStmnt (TimeCtrl d stat ) = genDelay d <> " " <> defMap stat @@ -209,9 +192,8 @@ genStmnt (TaskEnable task) = genTask task <> ";\n" genStmnt (SysTaskEnable task) = "$" <> genTask task <> ";\n" genTask :: Task -> Text -genTask (Task name expr) - | null expr = i - | otherwise = i <> "(" <> comma (genExpr <$> expr) <> ")" +genTask (Task name expr) | null expr = i + | otherwise = i <> "(" <> comma (genExpr <$> expr) <> ")" where i = name ^. getIdentifier -- | Render the 'Text' to 'IO'. This is equivalent to 'putStrLn'. diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs index 53d219b..f910924 100644 --- a/src/VeriFuzz/Verilog/Helpers.hs +++ b/src/VeriFuzz/Verilog/Helpers.hs @@ -45,9 +45,7 @@ testBench = ModDecl [ regDecl "a" , regDecl "b" , wireDecl "c" - , ModInst "and" - "and_gate" - [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"] + , ModInst "and" "and_gate" [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"] , Initial $ SeqBlock [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1 , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1 diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index bca1c39..9f22faa 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -25,9 +25,7 @@ import VeriFuzz.Verilog.CodeGen -- | Return if the 'Identifier' is in a 'ModDecl'. inPort :: Identifier -> ModDecl -> Bool inPort i m = inInput - where - inInput = - any (\a -> a ^. portName == i) $ m ^. modInPorts ++ m ^. modOutPorts + where inInput = any (\a -> a ^. portName == i) $ m ^. modInPorts ++ m ^. modOutPorts -- | Find the last assignment of a specific wire/reg to an expression, and -- returns that expression. @@ -59,8 +57,7 @@ replace = (transformOf traverseExpr .) . idTrans nestId :: Identifier -> ModDecl -> ModDecl nestId i m | not $ inPort i m - = let expr = fromMaybe def . findAssign i $ m ^. modItems - in m & get %~ replace i expr + = let expr = fromMaybe def . findAssign i $ m ^. modItems in m & get %~ replace i expr | otherwise = m where @@ -73,13 +70,10 @@ nestSource i src = src & getVerilogSrc . traverse . getDescription %~ nestId i -- | Nest variables in the format @w[0-9]*@ up to a certain number. nestUpTo :: Int -> VerilogSrc -> VerilogSrc -nestUpTo i src = - foldl (flip nestSource) src $ Identifier . fromNode <$> [1 .. i] +nestUpTo i src = foldl (flip nestSource) src $ Identifier . fromNode <$> [1 .. i] allVars :: ModDecl -> [Identifier] -allVars m = - (m ^.. modOutPorts . traverse . portName) - ++ (m ^.. modInPorts . traverse . portName) +allVars m = (m ^.. modOutPorts . traverse . portName) ++ (m ^.. modInPorts . traverse . portName) -- $setup -- >>> let m = (ModDecl (Identifier "m") [Port Wire 5 (Identifier "y")] [Port Wire 5 "x"] []) -- >>> let main = (ModDecl "main" [] [] []) @@ -100,16 +94,8 @@ instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++) where out = Decl Nothing <$> m ^. modOutPorts regIn = Decl Nothing <$> (m ^. modInPorts & traverse . portType .~ Reg False) - inst = ModInst (m ^. moduleId) - (m ^. moduleId <> (Identifier . showT $ count + 1)) - conns - count = - length - . filter (== m ^. moduleId) - $ main - ^.. modItems - . traverse - . modInstId + inst = ModInst (m ^. moduleId) (m ^. moduleId <> (Identifier . showT $ count + 1)) conns + count = length . filter (== m ^. moduleId) $ main ^.. modItems . traverse . modInstId conns = ModConn . Id <$> allVars m -- | Instantiate without adding wire declarations. It also does not count the @@ -151,9 +137,4 @@ makeTop i m = ModDecl (m ^. moduleId) ys (m ^. modInPorts) modIt where ys = Port Wire 90 . (flip makeIdFrom) "y" <$> [1 .. i] modIt = instantiateMod_ . modN <$> [1 .. i] - modN n = - m - & moduleId - %~ makeIdFrom n - & modOutPorts - .~ [Port Wire 90 (makeIdFrom n "y")] + modN n = m & moduleId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")] -- cgit