From 8109d52d387bd90052702a5a168ca9cf582766a0 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 17 Apr 2019 11:01:59 +0100 Subject: Fix other type errors and replace with Result type --- src/VeriFuzz.hs | 24 +++++++++++++------- src/VeriFuzz/Sim.hs | 3 --- src/VeriFuzz/Sim/Yosys.hs | 57 +++++++++++++++++++++++++++-------------------- 3 files changed, 49 insertions(+), 35 deletions(-) (limited to 'src') diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs index 88b0f63..18ddf34 100644 --- a/src/VeriFuzz.hs +++ b/src/VeriFuzz.hs @@ -36,9 +36,13 @@ import Hedgehog (Gen) import qualified Hedgehog.Gen as Hog import Prelude hiding (FilePath) import Shelly +import Shelly.Lifted (liftSh) import VeriFuzz.Circuit import VeriFuzz.Config +import VeriFuzz.Reduce +import VeriFuzz.Result import VeriFuzz.Sim +import VeriFuzz.Sim.Internal import VeriFuzz.Verilog -- | Generate a specific number of random bytestrings of size 256. @@ -81,23 +85,27 @@ runSimulation = do -- head $ (nestUpTo 30 . generateAST $ Circuit gr) ^.. getVerilog . traverse . getDescription rand <- generateByteString 20 rand2 <- Hog.sample (randomMod 10 100) - val <- shelly $ runSim defaultIcarus (makeSrcInfo rand2) rand - T.putStrLn $ showBS val + val <- shelly . runResultT $ runSim defaultIcarus (makeSrcInfo rand2) rand + case val of + Pass a -> T.putStrLn $ showBS a + _ -> T.putStrLn "Test failed" -- | Code to be executed on a failure. Also checks if the failure was a timeout, -- as the timeout command will return the 124 error code if that was the -- case. In that case, the error will be moved to a different directory. -onFailure :: Text -> RunFailed -> Sh () +onFailure :: Text -> RunFailed -> Sh (Result Failed ()) onFailure t _ = do ex <- lastExitCode case ex of 124 -> do echoP "Test TIMEOUT" chdir ".." $ cp_r (fromText t) $ fromText (t <> "_timeout") + return $ Fail EmptyFail _ -> do echoP "Test FAIL" chdir ".." $ cp_r (fromText t) $ fromText (t <> "_failed") + return $ Fail EmptyFail checkEquivalence :: SourceInfo -> Text -> IO Bool checkEquivalence src dir = shellyFailDir $ do @@ -106,7 +114,7 @@ checkEquivalence src dir = shellyFailDir $ do setenv "VERIFUZZ_ROOT" curr cd (fromText dir) catch_sh - ( runEquiv defaultYosys defaultYosys (Just defaultVivado) src + ( (runResultT $ runEquiv defaultYosys defaultYosys (Just defaultVivado) src) >> return True ) ((\_ -> return False) :: RunFailed -> Sh Bool) @@ -130,13 +138,13 @@ runEquivalence gm t d k i = do setenv "VERIFUZZ_ROOT" curr cd (fromText "output" fromText n) catch_sh - (runEquiv defaultYosys defaultYosys (Just defaultVivado) srcInfo - >> echoP "Test OK" + (runResultT $ runEquiv defaultYosys defaultYosys (Just defaultVivado) srcInfo + >> liftSh (echoP "Test OK") ) $ onFailure n catch_sh - ( runSim (Icarus "iverilog" "vvp") srcInfo rand - >>= (\b -> echoP ("RTL Sim: " <> showBS b)) + (runResultT $ runSim (Icarus "iverilog" "vvp") srcInfo rand + >>= (\b -> liftSh $ echoP ("RTL Sim: " <> showBS b)) ) $ onFailure n cd ".." diff --git a/src/VeriFuzz/Sim.hs b/src/VeriFuzz/Sim.hs index 9ccbbd8..b0905b7 100644 --- a/src/VeriFuzz/Sim.hs +++ b/src/VeriFuzz/Sim.hs @@ -25,8 +25,6 @@ module VeriFuzz.Sim -- ** XST , XST(..) , defaultXST - -- * Reducer - , reduce -- * Equivalence , runEquiv -- * Simulation @@ -39,7 +37,6 @@ where import VeriFuzz.Sim.Icarus import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Reduce import VeriFuzz.Sim.Vivado import VeriFuzz.Sim.XST import VeriFuzz.Sim.Yosys diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index 90a6ffd..3e1754a 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -23,6 +23,7 @@ where import Control.Lens import Prelude hiding (FilePath) import Shelly +import Shelly.Lifted (liftSh) import Text.Shakespeare.Text (st) import VeriFuzz.Sim.Internal import VeriFuzz.Sim.Template @@ -42,8 +43,8 @@ instance Synthesiser Yosys where defaultYosys :: Yosys defaultYosys = Yosys "yosys" -runSynthYosys :: Yosys -> SourceInfo -> FilePath -> Sh () -runSynthYosys sim (SourceInfo _ src) outf = do +runSynthYosys :: Yosys -> SourceInfo -> FilePath -> ResultSh () +runSynthYosys sim (SourceInfo _ src) outf = ( SynthFail) . liftSh $ do dir <- pwd writefile inpf $ genSource src echoP "Yosys: synthesis" @@ -57,11 +58,11 @@ runSynthYosys sim (SourceInfo _ src) outf = do inp = toTextIgnore inpf out = toTextIgnore outf -runMaybeSynth :: (Synthesiser a) => Maybe a -> SourceInfo -> Sh () +runMaybeSynth :: (Synthesiser a) => Maybe a -> SourceInfo -> ResultSh () runMaybeSynth (Just sim) srcInfo = runSynth sim srcInfo $ fromText [st|syn_#{toText sim}.v|] runMaybeSynth Nothing (SourceInfo _ src) = - writefile "syn_rtl.v" $ genSource src + liftSh . writefile "syn_rtl.v" $ genSource src runEquivYosys :: (Synthesiser a, Synthesiser b) @@ -69,15 +70,22 @@ runEquivYosys -> a -> Maybe b -> SourceInfo - -> Sh () + -> ResultSh () runEquivYosys yosys sim1 sim2 srcInfo = do - writefile "top.v" . genSource . initMod . makeTop 2 $ srcInfo ^. mainModule - writefile checkFile $ yosysSatConfig sim1 sim2 srcInfo + liftSh $ do + writefile "top.v" + . genSource + . initMod + . makeTop 2 + $ srcInfo + ^. mainModule + writefile checkFile $ yosysSatConfig sim1 sim2 srcInfo runSynth sim1 srcInfo $ fromText [st|syn_#{toText sim1}.v|] runMaybeSynth sim2 srcInfo - echoP "Yosys: equivalence check" - run_ (yosysPath yosys) [toTextIgnore checkFile] - echoP "Yosys: equivalence done" + liftSh $ do + echoP "Yosys: equivalence check" + run_ (yosysPath yosys) [toTextIgnore checkFile] + echoP "Yosys: equivalence done" where checkFile = fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|] @@ -88,20 +96,21 @@ runEquiv -> a -> Maybe b -> SourceInfo - -> Sh () + -> ResultSh () runEquiv _ sim1 sim2 srcInfo = do - root <- rootPath - dir <- pwd - echoP "SymbiYosys: setup" - writefile "top.v" - . genSource - . initMod - . makeTopAssert - $ srcInfo - ^. mainModule - writefile "test.sby" $ sbyConfig root sim1 sim2 srcInfo + root <- liftSh rootPath + dir <- liftSh pwd + liftSh $ do + echoP "SymbiYosys: setup" + writefile "top.v" + . genSource + . initMod + . makeTopAssert + $ srcInfo + ^. mainModule + writefile "test.sby" $ sbyConfig root sim1 sim2 srcInfo runSynth sim1 srcInfo $ fromText [st|syn_#{toText sim1}.v|] runMaybeSynth sim2 srcInfo - echoP "SymbiYosys: run" - logger_ dir "symbiyosys" $ run "sby" ["-f", "test.sby"] - echoP "SymbiYosys: done" + liftSh $ echoP "SymbiYosys: run" + execute_ EquivFail dir "symbiyosys" "sby" ["-f", "test.sby"] + liftSh $ echoP "SymbiYosys: done" -- cgit