From 983669aa390c4cc1aaf6e4bee914d1a7de9a58e4 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 10 Jan 2019 18:56:58 +0000 Subject: Fix all the warnings --- src/VeriFuzz/Graph/ASTGen.hs | 10 ++++---- src/VeriFuzz/Graph/CodeGen.hs | 3 +-- src/VeriFuzz/Graph/Random.hs | 2 +- src/VeriFuzz/Graph/RandomAlt.hs | 1 - src/VeriFuzz/Simulator/Xst.hs | 9 +++---- src/VeriFuzz/Verilog/CodeGen.hs | 52 ++++++++++++++++++++--------------------- src/VeriFuzz/Verilog/Helpers.hs | 3 +-- src/VeriFuzz/Verilog/Mutate.hs | 4 ++-- 8 files changed, 37 insertions(+), 47 deletions(-) (limited to 'src') diff --git a/src/VeriFuzz/Graph/ASTGen.hs b/src/VeriFuzz/Graph/ASTGen.hs index 2b241e1..f7bd058 100644 --- a/src/VeriFuzz/Graph/ASTGen.hs +++ b/src/VeriFuzz/Graph/ASTGen.hs @@ -16,10 +16,8 @@ import Data.Foldable (fold) import Data.Graph.Inductive (LNode, Node) import qualified Data.Graph.Inductive as G import Data.Maybe (catMaybes) -import qualified Data.Text as T import VeriFuzz.Circuit import VeriFuzz.Internal.Gen -import VeriFuzz.Internal.Shared import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.Helpers @@ -51,8 +49,8 @@ genPortsAST f c = -- | Generates the nested expression AST, so that it can then generate the -- assignment expressions. genAssignExpr :: Gate -> [Node] -> Maybe Expr -genAssignExpr g [] = Nothing -genAssignExpr g [n] = Just . Id $ frNode n +genAssignExpr _ [] = Nothing +genAssignExpr _ [n] = Just . Id $ frNode n genAssignExpr g (n:ns) = BinOp wire op <$> genAssignExpr g ns where wire = Id $ frNode n @@ -75,9 +73,9 @@ genAssignAST c = catMaybes $ genContAssignAST c <$> nodes nodes = G.labNodes gr genModuleDeclAST :: Circuit -> ModDecl -genModuleDeclAST c = ModDecl id output ports items +genModuleDeclAST c = ModDecl i output ports items where - id = Identifier "gen_module" + i = Identifier "gen_module" ports = genPortsAST inputsC c output = [Port Wire 90 "y"] items = genAssignAST c ++ [ModCA . ContAssign "y" . fold $ portToExpr <$> ports] diff --git a/src/VeriFuzz/Graph/CodeGen.hs b/src/VeriFuzz/Graph/CodeGen.hs index 0d23044..57e7b2a 100644 --- a/src/VeriFuzz/Graph/CodeGen.hs +++ b/src/VeriFuzz/Graph/CodeGen.hs @@ -15,8 +15,7 @@ module VeriFuzz.Graph.CodeGen ) where import Data.Foldable (fold) -import Data.Graph.Inductive (Graph, LNode, Node, indeg, labNodes, - nodes, outdeg, pre) +import Data.Graph.Inductive (Graph, LNode, Node, labNodes, pre) import Data.Maybe (fromMaybe) import Data.Text (Text) import qualified Data.Text as T diff --git a/src/VeriFuzz/Graph/Random.hs b/src/VeriFuzz/Graph/Random.hs index 0514f6d..ef0a0c5 100644 --- a/src/VeriFuzz/Graph/Random.hs +++ b/src/VeriFuzz/Graph/Random.hs @@ -12,7 +12,7 @@ Define the random generation for the directed acyclic graph. module VeriFuzz.Graph.Random where -import Data.Graph.Inductive (Context, Graph, LEdge) +import Data.Graph.Inductive (Context, LEdge) import qualified Data.Graph.Inductive as G import Data.Graph.Inductive.PatriciaTree (Gr) import Data.List (nub) diff --git a/src/VeriFuzz/Graph/RandomAlt.hs b/src/VeriFuzz/Graph/RandomAlt.hs index d9ee138..21ef678 100644 --- a/src/VeriFuzz/Graph/RandomAlt.hs +++ b/src/VeriFuzz/Graph/RandomAlt.hs @@ -12,7 +12,6 @@ Define the random generation for the directed acyclic graph. module VeriFuzz.Graph.RandomAlt where -import Data.Graph.Inductive (Graph, LEdge, mkGraph) import qualified Data.Graph.Inductive.Arbitrary as G import Data.Graph.Inductive.PatriciaTree (Gr) import Test.QuickCheck (Arbitrary, Gen) diff --git a/src/VeriFuzz/Simulator/Xst.hs b/src/VeriFuzz/Simulator/Xst.hs index 902b244..16e9b97 100644 --- a/src/VeriFuzz/Simulator/Xst.hs +++ b/src/VeriFuzz/Simulator/Xst.hs @@ -15,8 +15,6 @@ Xst (ise) simulator implementation. module VeriFuzz.Simulator.Xst where import Control.Lens hiding ((<.>)) -import Data.Text (Text) -import qualified Data.Text as T import Prelude hiding (FilePath) import Shelly import Text.Shakespeare.Text (st) @@ -38,7 +36,7 @@ defaultXst :: Xst defaultXst = Xst "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xst" "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/netgen" runSynthXst :: Xst -> ModDecl -> FilePath -> Sh () -runSynthXst sim mod outf = do +runSynthXst sim m outf = do writefile xstFile [st|run -ifn #{modName}.prj -ofn #{modName} -p artix7 -top #{modName} -iobuf NO -ram_extract NO -rom_extract NO -use_dsp48 NO @@ -46,13 +44,12 @@ runSynthXst sim mod outf = do -change_error_to_warning "HDLCompiler:226 HDLCompiler:1832" |] writefile prjFile [st|verilog work "rtl.v"|] - writefile "rtl.v" $ genSource mod + writefile "rtl.v" $ genSource m timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile] run_ (netgenPath sim) ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf] run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf] where - modName = mod ^. moduleId . getIdentifier + modName = m ^. moduleId . getIdentifier modFile = fromText modName xstFile = modFile <.> "xst" prjFile = modFile <.> "prj" - vFile = modFile <.> "v" diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index acbf15b..fbc2fc1 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -15,14 +15,12 @@ This module generates the code from the Verilog AST defined in module VeriFuzz.Verilog.CodeGen where -import Control.Lens (view, (^.)) -import Data.Foldable (fold) -import Data.Maybe (isNothing) -import Data.Text (Text) -import qualified Data.Text as T -import qualified Data.Text.IO as T -import Numeric (showHex) -import VeriFuzz.Internal.Shared +import Control.Lens (view, (^.)) +import Data.Foldable (fold) +import Data.Text (Text) +import qualified Data.Text as T +import qualified Data.Text.IO as T +import Numeric (showHex) import VeriFuzz.Verilog.AST -- | 'Source' class which determines that source code is able to be generated @@ -56,8 +54,8 @@ genDescription desc = -- | Generate the 'ModDecl' for a module and convert it to 'Text'. genModuleDecl :: ModDecl -> Text -genModuleDecl mod = - "module " <> mod ^. moduleId . getIdentifier +genModuleDecl m = + "module " <> m ^. moduleId . getIdentifier <> ports <> ";\n" <> modI <> "endmodule\n" @@ -65,10 +63,10 @@ genModuleDecl mod = ports | noIn && noOut = "" | otherwise = "(" <> comma (genModPort <$> outIn) <> ")" - modI = fold $ genModuleItem <$> mod ^. modItems - noOut = null $ mod ^. modOutPorts - noIn = null $ mod ^. modInPorts - outIn = (mod ^. modOutPorts) ++ (mod ^. modInPorts) + modI = fold $ genModuleItem <$> m ^. modItems + noOut = null $ m ^. modOutPorts + noIn = null $ m ^. modInPorts + outIn = (m ^. modOutPorts) ++ (m ^. modInPorts) -- | Conversts 'Port' to 'Text' for the module list, which means it only -- generates a list of identifiers. @@ -95,8 +93,8 @@ genPortDir PortInOut = "inout" -- | Generate a 'ModItem'. genModuleItem :: ModItem -> Text genModuleItem (ModCA ca) = genContAssign ca -genModuleItem (ModInst (Identifier id) (Identifier name) conn) = - id <> " " <> name <> "(" <> comma (genExpr . _modConn <$> conn) <> ")" <> ";\n" +genModuleItem (ModInst (Identifier i) (Identifier name) conn) = + i <> " " <> name <> "(" <> comma (genExpr . _modConn <$> conn) <> ")" <> ";\n" genModuleItem (Initial stat) = "initial " <> genStmnt stat genModuleItem (Always stat) = "always " <> genStmnt stat genModuleItem (Decl dir port) = @@ -114,8 +112,8 @@ genContAssign (ContAssign val e) = -- | Generate 'Expr' to 'Text'. genExpr :: Expr -> Text -genExpr (BinOp exprRhs bin exprLhs) = - "(" <> genExpr exprRhs <> genBinaryOperator bin <> genExpr exprLhs <> ")" +genExpr (BinOp eRhs bin eLhs) = + "(" <> genExpr eRhs <> genBinaryOperator bin <> genExpr eLhs <> ")" genExpr (Number s n) = showT s <> "'h" <> T.pack (showHex n "") genExpr (Id i) = i ^. getIdentifier @@ -169,7 +167,7 @@ genUnaryOperator UnNxorInv = "^~" -- | Generate verilog code for an 'Event'. genEvent :: Event -> Text -genEvent (EId id) = "@(" <> id ^. getIdentifier <> ")" +genEvent (EId i) = "@(" <> i ^. getIdentifier <> ")" genEvent (EExpr expr) = "@(" <> genExpr expr <> ")" genEvent EAll = "@*" @@ -179,11 +177,11 @@ genDelay (Delay i) = "#" <> showT i -- | Generate the verilog code for an 'LVal'. genLVal :: LVal -> Text -genLVal (RegId id) = id ^. getIdentifier -genLVal (RegExpr id expr) = - id ^. getIdentifier <> " [" <> genExpr expr <> "]" -genLVal (RegSize id msb lsb) = - id ^. getIdentifier <> " [" <> genConstExpr msb <> ":" <> genConstExpr lsb <> "]" +genLVal (RegId i) = i ^. getIdentifier +genLVal (RegExpr i expr) = + i ^. getIdentifier <> " [" <> genExpr expr <> "]" +genLVal (RegSize i msb lsb) = + i ^. getIdentifier <> " [" <> genConstExpr msb <> ":" <> genConstExpr lsb <> "]" genLVal (RegConcat e) = "{" <> comma (genExpr <$> e) <> "}" @@ -213,10 +211,10 @@ genStmnt (SysTaskEnable task) = "$" <> genTask task <> ";\n" genTask :: Task -> Text genTask (Task name expr) - | null expr = id - | otherwise = id <> "(" <> comma (genExpr <$> expr) <> ")" + | null expr = i + | otherwise = i <> "(" <> comma (genExpr <$> expr) <> ")" where - id = name ^. getIdentifier + i = name ^. getIdentifier -- | Render the 'Text' to 'IO'. This is equivalent to 'putStrLn'. render :: (Source a) => a -> IO () diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs index 90a5de4..554b8ba 100644 --- a/src/VeriFuzz/Verilog/Helpers.hs +++ b/src/VeriFuzz/Verilog/Helpers.hs @@ -14,7 +14,6 @@ module VeriFuzz.Verilog.Helpers where import Control.Lens import Data.Text (Text) -import qualified Data.Text import VeriFuzz.Verilog.AST regDecl :: Identifier -> ModItem @@ -69,4 +68,4 @@ defaultPort :: Identifier -> Port defaultPort = Port Wire 1 portToExpr :: Port -> Expr -portToExpr (Port _ _ id) = Id id +portToExpr (Port _ _ i) = Id i diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index dea5a66..eddb93a 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -139,10 +139,10 @@ makeIdFrom a i = -- modules to instantiate. makeTop :: Int -> ModDecl -> ModDecl makeTop i m = - ModDecl (m ^. moduleId) ys (m ^. modInPorts) modItems + ModDecl (m ^. moduleId) ys (m ^. modInPorts) modIt where ys = Port Wire 90 . (flip makeIdFrom) "y" <$> [1..i] - modItems = instantiateMod_ . modN <$> [1..i] + modIt = instantiateMod_ . modN <$> [1..i] modN n = m & moduleId %~ makeIdFrom n & modOutPorts .~ [Port Wire 90 (makeIdFrom n "y")] -- cgit