From 99d2932e1b4357f4e0aa303a29d08bfd81977a9e Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 1 Jan 2019 14:41:16 +0100 Subject: Formatting --- src/Test/VeriFuzz/Verilog/AST.hs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs index 288fb2e..6f6e930 100644 --- a/src/Test/VeriFuzz/Verilog/AST.hs +++ b/src/Test/VeriFuzz/Verilog/AST.hs @@ -210,9 +210,9 @@ data ContAssign = ContAssign { _contAssignNetLVal :: Identifier } deriving (Eq) -- | Stmnts in Verilog. -data Stmnt = TimeCtrl { _statDelay :: Delay - , _statDStat :: Maybe Stmnt - } -- ^ Time control (@#NUM@) +data Stmnt = TimeCtrl { _statDelay :: Delay + , _statDStat :: Maybe Stmnt + } -- ^ Time control (@#NUM@) | EventCtrl { _statEvent :: Event , _statEStat :: Maybe Stmnt } -- cgit