From 9db10c8914159106bc3da2efba87d74439b77361 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 1 Jan 2019 15:24:57 +0100 Subject: Add helper function to turn port into expr --- src/Test/VeriFuzz/Verilog/Helpers.hs | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs index b04aa76..20c3b0d 100644 --- a/src/Test/VeriFuzz/Verilog/Helpers.hs +++ b/src/Test/VeriFuzz/Verilog/Helpers.hs @@ -70,3 +70,6 @@ addTestBench = addDescription $ Description testBench defaultPort :: Identifier -> Port defaultPort = Port Wire 1 + +portToExpr :: Port -> Expr +portToExpr (Port _ _ id) = Id id -- cgit