From a5cfea8c673e2fe02951db078dbe030a63dd1c26 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Thu, 10 Jan 2019 17:49:02 +0000
Subject: Fix some imports

---
 src/VeriFuzz/Verilog/CodeGen.hs | 67 +++++++++--------------------------------
 1 file changed, 14 insertions(+), 53 deletions(-)

(limited to 'src')

diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs
index d97c8b9..8dc74a0 100644
--- a/src/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/VeriFuzz/Verilog/CodeGen.hs
@@ -11,9 +11,11 @@ This module generates the code from the Verilog AST defined in
 "VeriFuzz.Verilog.AST".
 -}
 
+{-# LANGUAGE FlexibleInstances #-}
+
 module VeriFuzz.Verilog.CodeGen where
 
-import           Control.Lens
+import           Control.Lens             (view, (^.))
 import           Data.Foldable            (fold)
 import           Data.Maybe               (isNothing)
 import           Data.Text                (Text)
@@ -23,6 +25,12 @@ import           Numeric                  (showHex)
 import           VeriFuzz.Internal.Shared
 import           VeriFuzz.Verilog.AST
 
+-- | 'Source' class which determines that source code is able to be generated
+-- from the data structure using 'genSource'. This will be stored in 'Text' and
+-- can then be processed further.
+class Source a where
+  genSource :: a -> Text
+
 -- | Inserts commas between '[Text]' and except the last one.
 comma :: [Text] -> Text
 comma = T.intercalate ", "
@@ -211,11 +219,14 @@ genTask (Task name expr)
     id = name ^. getIdentifier
 
 -- | Render the 'Text' to 'IO'. This is equivalent to 'putStrLn'.
-render :: Text -> IO ()
-render = T.putStrLn
+render :: (Source a) => a -> IO ()
+render = T.putStrLn . genSource
 
 -- Instances
 
+instance Source Identifier where
+  genSource = view getIdentifier
+
 instance Source Task where
   genSource = genTask
 
@@ -263,53 +274,3 @@ instance Source Description where
 
 instance Source VerilogSrc where
   genSource = genVerilogSrc
-
--- Show instances
-
-instance Show Task where
-  show = T.unpack . genTask
-
-instance Show Stmnt where
-  show = T.unpack . genStmnt
-
-instance Show PortType where
-  show = T.unpack . genPortType
-
-instance Show ConstExpr where
-  show = T.unpack . genConstExpr
-
-instance Show LVal where
-  show = T.unpack . genLVal
-
-instance Show Delay where
-  show = T.unpack . genDelay
-
-instance Show Event where
-  show = T.unpack . genEvent
-
-instance Show UnaryOperator where
-  show = T.unpack . genUnaryOperator
-
-instance Show Expr where
-  show = T.unpack . genExpr
-
-instance Show ContAssign where
-  show = T.unpack . genContAssign
-
-instance Show ModItem where
-  show = T.unpack . genModuleItem
-
-instance Show PortDir where
-  show = T.unpack . genPortDir
-
-instance Show Port where
-  show = T.unpack . genPort
-
-instance Show ModDecl where
-  show = T.unpack . genModuleDecl
-
-instance Show Description where
-  show = T.unpack . genDescription
-
-instance Show VerilogSrc where
-  show = T.unpack . genVerilogSrc
-- 
cgit