From ae4497bee80efbabddea9333732f783433ff4a5a Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 2 Apr 2019 13:05:16 +0100 Subject: Make GenVerilog part of Arb --- src/VeriFuzz/CodeGen.hs | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/VeriFuzz/CodeGen.hs b/src/VeriFuzz/CodeGen.hs index f122fa5..5b27fea 100644 --- a/src/VeriFuzz/CodeGen.hs +++ b/src/VeriFuzz/CodeGen.hs @@ -27,7 +27,6 @@ import Data.Text (Text) import qualified Data.Text as T import qualified Data.Text.IO as T import Numeric (showHex) -import Test.QuickCheck (Arbitrary, arbitrary) import VeriFuzz.AST import VeriFuzz.Internal @@ -286,8 +285,8 @@ newtype GenVerilog a = GenVerilog { unGenVerilog :: a } instance (Source a) => Show (GenVerilog a) where show = T.unpack . genSource . unGenVerilog -instance (Arbitrary a) => Arbitrary (GenVerilog a) where - arbitrary = GenVerilog <$> arbitrary +instance (Arb a) => Arb (GenVerilog a) where + arb = GenVerilog <$> arb instance Source SourceInfo where genSource (SourceInfo _ src) = genSource src -- cgit