From af7f1a5522d90bccfb16ca0d7f9f8726f419a113 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sat, 15 Dec 2018 20:18:22 +0000
Subject: Add AST generation

---
 src/Test/VeriFuzz/Graph/ASTGen.hs | 47 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 src/Test/VeriFuzz/Graph/ASTGen.hs

(limited to 'src')

diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs
new file mode 100644
index 0000000..f481c24
--- /dev/null
+++ b/src/Test/VeriFuzz/Graph/ASTGen.hs
@@ -0,0 +1,47 @@
+{-|
+Module      : Test.VeriFuzz.Graph.ASTGen
+Description : Generates the AST from the graph directly.
+Copyright   : (c) Yann Herklotz Grave 2018
+License     : GPL-3
+Maintainer  : ymherklotz@gmail.com
+Stability   : experimental
+Portability : POSIX
+
+Generates the AST from the graph directly.
+-}
+
+{-# LANGUAGE OverloadedStrings #-}
+
+module Test.VeriFuzz.Graph.ASTGen where
+
+import qualified Data.Graph.Inductive     as G
+import qualified Data.Text                as T
+import           Test.VeriFuzz.Circuit
+import           Test.VeriFuzz.VerilogAST
+
+fromNode :: G.Node -> Identifier
+fromNode node = Identifier . T.pack $ "w" <> show node
+
+filterGr :: (G.Graph gr) => gr n e -> (G.Node -> Bool) -> [G.Node]
+filterGr graph f =
+  filter f $ G.nodes graph
+
+genPortsAST :: Circuit -> [Port]
+genPortsAST c = ((Port Input . fromNode) <$> inp) ++ ((Port Output) . fromNode <$> out)
+  where
+    zero fun1 fun2 n = fun1 graph n == 0 && fun2 graph n /= 0
+    inp = filterGr graph $ zero G.indeg G.outdeg
+    out = filterGr graph $ zero G.outdeg G.indeg
+    graph = getCircuit c
+
+genModuleDeclAST :: Circuit -> ModuleDecl
+genModuleDeclAST c =
+  ModuleDecl id ports items
+  where
+    id = Identifier "gen_module"
+    ports = genPortsAST c
+    items = []
+
+generateAST :: Circuit -> SourceText
+generateAST c =
+  SourceText [Description $ genModuleDeclAST c]
-- 
cgit