From b25eee73ce7cf8270ccf633443cee88040eaca67 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sun, 30 Dec 2018 12:03:11 +0100 Subject: Move helper functions --- src/Test/VeriFuzz.hs | 3 -- src/Test/VeriFuzz/Helpers.hs | 73 ---------------------------------- src/Test/VeriFuzz/Verilog.hs | 2 + src/Test/VeriFuzz/Verilog/Helpers.hs | 76 ++++++++++++++++++++++++++++++++++++ 4 files changed, 78 insertions(+), 76 deletions(-) delete mode 100644 src/Test/VeriFuzz/Helpers.hs create mode 100644 src/Test/VeriFuzz/Verilog/Helpers.hs (limited to 'src') diff --git a/src/Test/VeriFuzz.hs b/src/Test/VeriFuzz.hs index a16b095..a3204b3 100644 --- a/src/Test/VeriFuzz.hs +++ b/src/Test/VeriFuzz.hs @@ -14,8 +14,6 @@ module Test.VeriFuzz module Test.VeriFuzz.Circuit -- * Verilog AST Data Types , module Test.VeriFuzz.Verilog - -- * Helpers - , module Test.VeriFuzz.Helpers -- * Graphs , module Test.VeriFuzz.Graph.ASTGen , module Test.VeriFuzz.Graph.CodeGen @@ -28,6 +26,5 @@ import Test.VeriFuzz.Circuit import Test.VeriFuzz.Graph.ASTGen import Test.VeriFuzz.Graph.CodeGen import Test.VeriFuzz.Graph.Random -import Test.VeriFuzz.Helpers import Test.VeriFuzz.Simulator import Test.VeriFuzz.Verilog diff --git a/src/Test/VeriFuzz/Helpers.hs b/src/Test/VeriFuzz/Helpers.hs deleted file mode 100644 index 6643683..0000000 --- a/src/Test/VeriFuzz/Helpers.hs +++ /dev/null @@ -1,73 +0,0 @@ -{-| -Module : Test.VeriFuzz.Default -Description : Defaults and common functions. -Copyright : (c) 2018-2019, Yann Herklotz Grave -License : BSD-3 -Maintainer : ymherklotz [at] gmail [dot] com -Stability : experimental -Portability : POSIX - -Defaults and common functions. --} - -module Test.VeriFuzz.Helpers where - -import Control.Lens -import Data.Text (Text) -import qualified Data.Text -import Test.VeriFuzz.Verilog.AST - -regDecl :: Text -> ModItem -regDecl = Decl . Port (Reg False) . Identifier - -wireDecl :: Text -> ModItem -wireDecl = Decl . Port (PortNet Wire) . Identifier - -modConn :: Text -> ModConn -modConn = ModConn . PrimExpr . PrimId . Identifier - --- | Create a number expression which will be stored in a primary expression. -numExpr :: Int -> Int -> Expression -numExpr = ((PrimExpr . PrimNum) .) . Number - --- | Create an empty module. -emptyMod :: ModDecl -emptyMod = ModDecl "" Nothing [] [] - --- | Set a module name for a module declaration. -setModName :: Text -> ModDecl -> ModDecl -setModName str = moduleId .~ Identifier str - --- | Add a input port to the module declaration. -addModPort :: Port -> ModDecl -> ModDecl -addModPort port = modInPorts %~ (:) port - -addDescription :: Description -> VerilogSrc -> VerilogSrc -addDescription desc = getVerilogSrc %~ (:) desc - -testBench :: ModDecl -testBench = - ModDecl "main" Nothing [] - [ regDecl "a" - , regDecl "b" - , wireDecl "c" - , ModInst "and" "and_gate" - [ modConn "c" - , modConn "a" - , modConn "b" - ] - , Initial $ SeqBlock - [ BlockAssign . Assign (RegId "a") Nothing . PrimExpr . PrimNum $ Number 1 1 - , BlockAssign . Assign (RegId "b") Nothing . PrimExpr . PrimNum $ Number 1 1 - -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display" - -- [ ExprStr "%d & %d = %d" - -- , PrimExpr $ PrimId "a" - -- , PrimExpr $ PrimId "b" - -- , PrimExpr $ PrimId "c" - -- ] - -- , SysTaskEnable $ Task "finish" [] - ] - ] - -addTestBench :: VerilogSrc -> VerilogSrc -addTestBench = addDescription $ Description testBench diff --git a/src/Test/VeriFuzz/Verilog.hs b/src/Test/VeriFuzz/Verilog.hs index 3fa4747..072dc75 100644 --- a/src/Test/VeriFuzz/Verilog.hs +++ b/src/Test/VeriFuzz/Verilog.hs @@ -17,8 +17,10 @@ module Test.VeriFuzz.Verilog , module Test.VeriFuzz.Verilog.CodeGen -- * Verilog mutations , module Test.VeriFuzz.Verilog.Mutate + , module Test.VeriFuzz.Verilog.Helpers ) where import Test.VeriFuzz.Verilog.AST import Test.VeriFuzz.Verilog.CodeGen +import Test.VeriFuzz.Verilog.Helpers import Test.VeriFuzz.Verilog.Mutate diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs new file mode 100644 index 0000000..d4a7c9c --- /dev/null +++ b/src/Test/VeriFuzz/Verilog/Helpers.hs @@ -0,0 +1,76 @@ +{-| +Module : Test.VeriFuzz.VeriFuzz.Helpers +Description : Defaults and common functions. +Copyright : (c) 2018-2019, Yann Herklotz Grave +License : BSD-3 +Maintainer : ymherklotz [at] gmail [dot] com +Stability : experimental +Portability : POSIX + +Defaults and common functions. +-} + +module Test.VeriFuzz.VeriFuzz.Helpers where + +import Control.Lens +import Data.Text (Text) +import qualified Data.Text +import Test.VeriFuzz.Verilog.AST + +regDecl :: Text -> ModItem +regDecl = Decl . Port (Reg False) . Identifier + +wireDecl :: Text -> ModItem +wireDecl = Decl . Port (PortNet Wire) . Identifier + +modConn :: Text -> ModConn +modConn = ModConn . PrimExpr . PrimId . Identifier + +-- | Create a number expression which will be stored in a primary expression. +numExpr :: Int -> Int -> Expression +numExpr = ((PrimExpr . PrimNum) .) . Number + +-- | Create an empty module. +emptyMod :: ModDecl +emptyMod = ModDecl "" Nothing [] [] + +-- | Set a module name for a module declaration. +setModName :: Text -> ModDecl -> ModDecl +setModName str = moduleId .~ Identifier str + +-- | Add a input port to the module declaration. +addModPort :: Port -> ModDecl -> ModDecl +addModPort port = modInPorts %~ (:) port + +addDescription :: Description -> VerilogSrc -> VerilogSrc +addDescription desc = getVerilogSrc %~ (:) desc + +testBench :: ModDecl +testBench = + ModDecl "main" Nothing [] + [ regDecl "a" + , regDecl "b" + , wireDecl "c" + , ModInst "and" "and_gate" + [ modConn "c" + , modConn "a" + , modConn "b" + ] + , Initial $ SeqBlock + [ BlockAssign . Assign (RegId "a") Nothing . PrimExpr . PrimNum $ Number 1 1 + , BlockAssign . Assign (RegId "b") Nothing . PrimExpr . PrimNum $ Number 1 1 + -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display" + -- [ ExprStr "%d & %d = %d" + -- , PrimExpr $ PrimId "a" + -- , PrimExpr $ PrimId "b" + -- , PrimExpr $ PrimId "c" + -- ] + -- , SysTaskEnable $ Task "finish" [] + ] + ] + +addTestBench :: VerilogSrc -> VerilogSrc +addTestBench = addDescription $ Description testBench + +defaultPort :: Identifier -> Port +defaultPort = Port (PortNet Wire) 1 -- cgit