From b4b1d0dcb0864c25275fdcc1ccd93a4dfaae51a1 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 4 Apr 2019 15:30:52 +0100 Subject: Better formatting for if-statement --- src/VeriFuzz/Verilog/CodeGen.hs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index eb3b3d1..a05309f 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -215,9 +215,9 @@ statement (NonBlockAssign a ) = genAssign " <= " a <> ";\n" statement (StatCA a ) = contAssign a statement (TaskEnable t ) = task t <> ";\n" statement (SysTaskEnable t ) = "$" <> task t <> ";\n" -statement (CondStmnt e t Nothing) = "if(" <> expr e <> ")" <> defMap t +statement (CondStmnt e t Nothing) = "if(" <> expr e <> ")\n" <> defMap t statement (CondStmnt e t f) = - "if(" <> expr e <> ") " <> defMap t <> "else " <> defMap f + "if(" <> expr e <> ")\n" <> defMap t <> "else\n" <> defMap f task :: Task -> Text task (Task name e) | null e = i -- cgit