From b679d2c6b19f647a3af98019426dfd05e8e103e9 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Mon, 31 Dec 2018 13:06:56 +0100
Subject: Finish module instantiation

---
 src/Test/VeriFuzz/Verilog/AST.hs    |  6 ++++++
 src/Test/VeriFuzz/Verilog/Mutate.hs | 15 ++++++++++-----
 2 files changed, 16 insertions(+), 5 deletions(-)

(limited to 'src')

diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs
index 3ae595f..85c3e99 100644
--- a/src/Test/VeriFuzz/Verilog/AST.hs
+++ b/src/Test/VeriFuzz/Verilog/AST.hs
@@ -385,6 +385,12 @@ instance QC.Arbitrary VerilogSrc where
 instance IsString Identifier where
   fromString = Identifier . T.pack
 
+instance Semigroup Identifier where
+  (Identifier a) <> (Identifier b) = Identifier (a <> b)
+
+instance Monoid Identifier where
+  mempty = Identifier mempty
+
 -- Traversal Instance
 
 traverseExpr :: Traversal' Expression Expression
diff --git a/src/Test/VeriFuzz/Verilog/Mutate.hs b/src/Test/VeriFuzz/Verilog/Mutate.hs
index 847d890..1d58007 100644
--- a/src/Test/VeriFuzz/Verilog/Mutate.hs
+++ b/src/Test/VeriFuzz/Verilog/Mutate.hs
@@ -20,10 +20,6 @@ import           Test.VeriFuzz.Internal.Shared
 import           Test.VeriFuzz.Verilog.AST
 import           Test.VeriFuzz.Verilog.CodeGen
 
--- $setup
--- >>> let mod = (ModDecl (Identifier "m") [Port (PortNet Wire) 5 (Identifier "y")] [Port (PortNet Wire) 5 "x"] [])
--- >>> let main = (ModDecl "main" [] [] [])
-
 -- | Return if the 'Identifier' is in a 'ModDecl'.
 inPort :: Identifier -> ModDecl -> Bool
 inPort id mod = inInput
@@ -80,6 +76,10 @@ nestUpTo :: Int -> VerilogSrc -> VerilogSrc
 nestUpTo i src =
   foldl (flip nestSource) src $ Identifier . fromNode <$> [1..i]
 
+-- $setup
+-- >>> let mod = (ModDecl (Identifier "m") [Port (PortNet Wire) 5 (Identifier "y")] [Port (PortNet Wire) 5 "x"] [])
+-- >>> let main = (ModDecl "main" [] [] [])
+
 -- | Add a Module Instantiation using 'ModInst' from the first module passed to
 -- it to the body of the second module. It first has to make all the inputs into
 -- @reg@.
@@ -88,14 +88,19 @@ nestUpTo i src =
 -- module main;
 -- wire [4:0] y;
 -- reg [4:0] x;
+-- m m1(y, x);
 -- endmodule
 -- <BLANKLINE>
 instantiateMod :: ModDecl -> ModDecl -> ModDecl
 instantiateMod mod main =
-  main & moduleItems %~ ((out ++ regIn)++)
+  main & moduleItems %~ ((out ++ regIn ++ [inst])++)
   where
     out = Decl Nothing <$> mod ^. modOutPorts
     regIn = Decl Nothing <$> (mod ^. modInPorts & traverse . portType .~ Reg False)
+    inst = ModInst (mod ^. moduleId) (mod ^. moduleId <> (Identifier . showT $ count+1)) conns
+    count = length . filter (==mod ^. moduleId) $ main ^.. moduleItems . traverse . modInstId
+    conns = ModConn . PrimExpr . PrimId <$>
+      (mod ^.. modOutPorts . traverse . portName) ++ (mod ^.. modInPorts . traverse . portName)
 
 -- | Initialise all the inputs and outputs to a module.
 --
-- 
cgit