From cedff4da4ee36ed6b3b4c1c20012d96075a87a9f Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 1 Feb 2019 19:48:02 +0000 Subject: Rename XST and add imports --- src/VeriFuzz.hs | 48 +++++++++++++++++++++++++++----------------- src/VeriFuzz/XST.hs | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++ src/VeriFuzz/Xst.hs | 57 ----------------------------------------------------- 3 files changed, 87 insertions(+), 75 deletions(-) create mode 100644 src/VeriFuzz/XST.hs delete mode 100644 src/VeriFuzz/Xst.hs (limited to 'src') diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs index fecc5d2..edf561b 100644 --- a/src/VeriFuzz.hs +++ b/src/VeriFuzz.hs @@ -9,23 +9,35 @@ Portability : POSIX -} module VeriFuzz - ( - -- * Definitions - module VeriFuzz.Circuit - -- * Verilog AST Data Types - , module VeriFuzz.Verilog - -- * Graphs - , module VeriFuzz.Graph.ASTGen - , module VeriFuzz.Graph.CodeGen - , module VeriFuzz.Graph.Random - -- * Simulator - , module VeriFuzz.Simulator - ) -where + ( module VeriFuzz.AST + , module VeriFuzz.ASTGen + , module VeriFuzz.Circuit + , module VeriFuzz.CodeGen + , module VeriFuzz.Env + , module VeriFuzz.Gen + , module VeriFuzz.General + , module VeriFuzz.Helpers + , module VeriFuzz.Icarus + , module VeriFuzz.Internal + , module VeriFuzz.Mutate + , module VeriFuzz.Random + , module VeriFuzz.RandomAlt + , module VeriFuzz.XST + , module VeriFuzz.Yosys + ) where +import VeriFuzz.AST +import VeriFuzz.ASTGen import VeriFuzz.Circuit -import VeriFuzz.Graph.ASTGen -import VeriFuzz.Graph.CodeGen -import VeriFuzz.Graph.Random -import VeriFuzz.Simulator -import VeriFuzz.Verilog +import VeriFuzz.CodeGen +import VeriFuzz.Env +import VeriFuzz.Gen +import VeriFuzz.General +import VeriFuzz.Helpers +import VeriFuzz.Icarus +import VeriFuzz.Internal +import VeriFuzz.Mutate +import VeriFuzz.Random +import VeriFuzz.RandomAlt +import VeriFuzz.XST +import VeriFuzz.Yosys diff --git a/src/VeriFuzz/XST.hs b/src/VeriFuzz/XST.hs new file mode 100644 index 0000000..1cd63eb --- /dev/null +++ b/src/VeriFuzz/XST.hs @@ -0,0 +1,57 @@ +{-| +Module : VeriFuzz.Simulator.XST +Description : Xst (ise) simulator implementation. +Copyright : (c) 2018-2019, Yann Herklotz Grave +License : BSD-3 +Maintainer : ymherklotz [at] gmail [dot] com +Stability : experimental +Portability : POSIX + +Xst (ise) simulator implementation. +-} + +{-# LANGUAGE QuasiQuotes #-} + +module VeriFuzz.Simulator.XST where + +import Control.Lens hiding ((<.>)) +import qualified Data.Text as T +import Prelude hiding (FilePath) +import Shelly +import System.FilePath.Posix (takeBaseName) +import Text.Shakespeare.Text (st) +import VeriFuzz.Simulator.General +import VeriFuzz.Simulator.Internal.Template +import VeriFuzz.Verilog +import VeriFuzz.Verilog + +data Xst = Xst { xstPath :: FilePath + , netgenPath :: FilePath + } + +instance Simulator Xst where + toText _ = "xst" + +instance Synthesize Xst where + runSynth = runSynthXst + +defaultXst :: Xst +defaultXst = + Xst "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xst" "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/netgen" + +runSynthXst :: Xst -> ModDecl -> FilePath -> Sh () +runSynthXst sim m outf = do + writefile xstFile $ xstSynthConfig m + writefile prjFile [st|verilog work "rtl.v"|] + writefile "rtl.v" $ genSource m + echoP "Run xst" + noPrint $ timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile] + echoP "Run netgen" + noPrint $ run_ (netgenPath sim) + ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf] + echoP "Clean synthesized file" + noPrint $ run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf] + where + modFile = fromText $ modName m + xstFile = modFile <.> "xst" + prjFile = modFile <.> "prj" diff --git a/src/VeriFuzz/Xst.hs b/src/VeriFuzz/Xst.hs deleted file mode 100644 index 52272c3..0000000 --- a/src/VeriFuzz/Xst.hs +++ /dev/null @@ -1,57 +0,0 @@ -{-| -Module : VeriFuzz.Simulator.Xst -Description : Xst (ise) simulator implementation. -Copyright : (c) 2018-2019, Yann Herklotz Grave -License : BSD-3 -Maintainer : ymherklotz [at] gmail [dot] com -Stability : experimental -Portability : POSIX - -Xst (ise) simulator implementation. --} - -{-# LANGUAGE QuasiQuotes #-} - -module VeriFuzz.Simulator.Xst where - -import Control.Lens hiding ((<.>)) -import qualified Data.Text as T -import Prelude hiding (FilePath) -import Shelly -import System.FilePath.Posix (takeBaseName) -import Text.Shakespeare.Text (st) -import VeriFuzz.Simulator.General -import VeriFuzz.Simulator.Internal.Template -import VeriFuzz.Verilog -import VeriFuzz.Verilog - -data Xst = Xst { xstPath :: FilePath - , netgenPath :: FilePath - } - -instance Simulator Xst where - toText _ = "xst" - -instance Synthesize Xst where - runSynth = runSynthXst - -defaultXst :: Xst -defaultXst = - Xst "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xst" "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/netgen" - -runSynthXst :: Xst -> ModDecl -> FilePath -> Sh () -runSynthXst sim m outf = do - writefile xstFile $ xstSynthConfig m - writefile prjFile [st|verilog work "rtl.v"|] - writefile "rtl.v" $ genSource m - echoP "Run xst" - noPrint $ timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile] - echoP "Run netgen" - noPrint $ run_ (netgenPath sim) - ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf] - echoP "Clean synthesized file" - noPrint $ run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf] - where - modFile = fromText $ modName m - xstFile = modFile <.> "xst" - prjFile = modFile <.> "prj" -- cgit