From db5b066ad6ad7e05295209ffd8f003a6d5b6bb5a Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 2 Jan 2019 11:28:42 +0100 Subject: Fix indentation --- src/Test/VeriFuzz/Verilog/AST.hs | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs index 4f2c52d..184390e 100644 --- a/src/Test/VeriFuzz/Verilog/AST.hs +++ b/src/Test/VeriFuzz/Verilog/AST.hs @@ -213,16 +213,16 @@ data ContAssign = ContAssign { _contAssignNetLVal :: Identifier data Stmnt = TimeCtrl { _statDelay :: Delay , _statDStat :: Maybe Stmnt } -- ^ Time control (@#NUM@) - | EventCtrl { _statEvent :: Event - , _statEStat :: Maybe Stmnt - } - | SeqBlock { _statements :: [Stmnt] } -- ^ Sequential block (@begin ... end@) - | BlockAssign Assign -- ^ blocking assignment (@=@) - | NonBlockAssign Assign -- ^ Non blocking assignment (@<=@) - | StatCA ContAssign -- ^ Stmnt continuous assignment. May not be correct. - | TaskEnable Task - | SysTaskEnable Task - deriving (Eq) + | EventCtrl { _statEvent :: Event + , _statEStat :: Maybe Stmnt + } + | SeqBlock { _statements :: [Stmnt] } -- ^ Sequential block (@begin ... end@) + | BlockAssign Assign -- ^ blocking assignment (@=@) + | NonBlockAssign Assign -- ^ Non blocking assignment (@<=@) + | StatCA ContAssign -- ^ Stmnt continuous assignment. May not be correct. + | TaskEnable Task + | SysTaskEnable Task + deriving (Eq) instance Semigroup Stmnt where (SeqBlock a) <> (SeqBlock b) = SeqBlock $ a <> b -- cgit