From e7f7d1988ad9a161ba10e36859dc04a92422a4e0 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Wed, 7 Nov 2018 14:44:39 +0000
Subject: Add simple verilog AND gate

---
 src/Main.hs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/Main.hs b/src/Main.hs
index 6aff865..bc80b49 100644
--- a/src/Main.hs
+++ b/src/Main.hs
@@ -34,5 +34,5 @@ main :: IO FilePath
 --main = sample (arbitrary :: Gen (Circuit Input))
 main = do
   gen <- withSystemRandom . asGenIO $ return
-  gr <- wattsStrogatzGraph gen 50 3 0.6
+  gr <- wattsStrogatzGraph gen 100 2 0.6
   runGraphviz (graphToDot nonClusteredParams (graphInfoToUGr gr)) Png "output.png"
-- 
cgit