From f0cc5bb8865b039b18bdc89e81df9bad72e0bdb5 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sat, 29 Dec 2018 01:56:22 +0100 Subject: Add simulator code --- src/Test/VeriFuzz/Simulator/General.hs | 24 ++++++++++++++++++------ src/Test/VeriFuzz/Simulator/Icarus.hs | 4 +++- src/Test/VeriFuzz/Simulator/Yosys.hs | 4 +++- 3 files changed, 24 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/Test/VeriFuzz/Simulator/General.hs b/src/Test/VeriFuzz/Simulator/General.hs index d52b7cd..c7dfd99 100644 --- a/src/Test/VeriFuzz/Simulator/General.hs +++ b/src/Test/VeriFuzz/Simulator/General.hs @@ -12,9 +12,18 @@ Class of the simulator and the synthesize tool. module Test.VeriFuzz.Simulator.General where -import Data.Text (Text) -import Prelude hiding (FilePath) +import Data.ByteString.Builder (byteStringHex, toLazyByteString) +import Data.ByteString.Char8 (ByteString) +import qualified Data.ByteString.Char8 as B +import qualified Data.ByteString.Lazy.Char8 as BL +import Data.Text (Text) +import qualified Data.Text as T +import qualified Data.Text.Lazy as TL +import Data.Text.Lazy.Builder (toLazyText) +import Data.Text.Lazy.Builder.Int (hexadecimal) +import Prelude hiding (FilePath) import Shelly +import Test.VeriFuzz.Internal.Shared import Test.VeriFuzz.Verilog.AST -- | Simulator class. @@ -23,10 +32,10 @@ class Simulator a where -- | Simulation type class. class (Simulator a) => Simulate a where - runSim :: a -- ^ Simulator instance - -> ModDecl -- ^ Module to simulate - -> [Int] -- ^ Inputs to simulate - -> Sh Int -- ^ Returns the value of the hash at the output of the testbench + runSim :: a -- ^ Simulator instance + -> ModDecl -- ^ Module to simulate + -> [ByteString] -- ^ Inputs to simulate + -> Sh Int -- ^ Returns the value of the hash at the output of the testbench. -- | Synthesize type class. class (Simulator a) => Synthesize a where @@ -46,3 +55,6 @@ synthesizers = ["yosys", "xst"] simulators :: [Text] simulators = ["yosim", "iverilog"] + +toHex :: ByteString -> Text +toHex bs = T.pack . BL.unpack . toLazyByteString $ byteStringHex bs diff --git a/src/Test/VeriFuzz/Simulator/Icarus.hs b/src/Test/VeriFuzz/Simulator/Icarus.hs index eaf7aff..119544f 100644 --- a/src/Test/VeriFuzz/Simulator/Icarus.hs +++ b/src/Test/VeriFuzz/Simulator/Icarus.hs @@ -14,6 +14,8 @@ Icarus verilog module. module Test.VeriFuzz.Simulator.Icarus where +import Data.ByteString (ByteString) +import qualified Data.ByteString as B import Data.Text (Text) import qualified Data.Text as T import Prelude hiding (FilePath) @@ -31,5 +33,5 @@ instance Simulator Icarus where instance Simulate Icarus where runSim = runSimIcarus -runSimIcarus :: Icarus -> ModDecl -> [Int] -> Sh Int +runSimIcarus :: Icarus -> ModDecl -> [ByteString] -> Sh Int runSimIcarus sim mod inp = return 0 diff --git a/src/Test/VeriFuzz/Simulator/Yosys.hs b/src/Test/VeriFuzz/Simulator/Yosys.hs index a3034eb..778918d 100644 --- a/src/Test/VeriFuzz/Simulator/Yosys.hs +++ b/src/Test/VeriFuzz/Simulator/Yosys.hs @@ -14,6 +14,8 @@ Yosys simulator implementation. module Test.VeriFuzz.Simulator.Yosys where +import Data.ByteString (ByteString) +import qualified Data.ByteString as B import Data.Text (Text) import qualified Data.Text as T import Prelude hiding (FilePath) @@ -44,7 +46,7 @@ writeSimFile sim mod file = do rename mod mod_rtl |] -runSimYosys :: Yosys -> ModDecl -> [Int] -> Sh Int +runSimYosys :: Yosys -> ModDecl -> [ByteString] -> Sh Int runSimYosys sim ver tb = return 0 runSynthYosys :: Yosys -> ModDecl -> FilePath -> Sh () -- cgit