From 9a051648695d459d4564be58ae4850e159cb3ba3 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Sun, 19 May 2019 18:17:10 +0100
Subject: Change simple graph check to acyclic check

---
 test/Property.hs | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

(limited to 'test/Property.hs')

diff --git a/test/Property.hs b/test/Property.hs
index 7b1771c..001c7d3 100644
--- a/test/Property.hs
+++ b/test/Property.hs
@@ -32,11 +32,18 @@ import           VeriFuzz.Verilog.Parser
 randomDAG' :: Gen Circuit
 randomDAG' = Hog.resize 30 randomDAG
 
-simpleGraph :: Property
-simpleGraph = Hog.property $ do
+acyclicGraph :: Property
+acyclicGraph = Hog.property $ do
     xs <- Hog.forAllWith (const "") randomDAG'
     Hog.assert $ simp xs
-    where simp = G.isSimple . getCircuit
+  where
+    simp g =
+        (== G.noNodes (getCircuit g))
+            . sum
+            . fmap length
+            . G.scc
+            . getCircuit
+            $ g
 
 type GenFunctor f a b c =
     ( Functor f
@@ -76,7 +83,7 @@ propertyResultInterrupted = do
 propertyTests :: TestTree
 propertyTests = testGroup
     "Property Tests"
-    [ testProperty "simple graph generation check" simpleGraph
-    , testProperty "fmap for Result"               propertyResultInterrupted
+    [ testProperty "acyclic graph generation check" acyclicGraph
+    , testProperty "fmap for Result"                propertyResultInterrupted
     , parserTests
     ]
-- 
cgit