From 1e4798b9bfe090ac68c2edd036637b6bfac5c06b Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 6 May 2019 18:59:08 +0100 Subject: Support multiple reg assigns in if statements --- test/Property.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'test') diff --git a/test/Property.hs b/test/Property.hs index f7c6865..fe802c9 100644 --- a/test/Property.hs +++ b/test/Property.hs @@ -23,7 +23,7 @@ import qualified Hedgehog.Range as Hog import Test.Tasty import Test.Tasty.Hedgehog import Text.Parsec -import VeriFuzz +import VeriFuzz hiding (Property) import VeriFuzz.Result import VeriFuzz.Verilog.Lex import VeriFuzz.Verilog.Parser -- cgit