From 14158fc4ef0809adbbf0b7fdd0c0d5e0fafc2435 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Fri, 24 May 2019 15:45:35 +0100 Subject: Fix used wire check for clk --- test/Reduce.hs | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'test') diff --git a/test/Reduce.hs b/test/Reduce.hs index 9c59e48..bc4bbc3 100644 --- a/test/Reduce.hs +++ b/test/Reduce.hs @@ -52,6 +52,7 @@ module top; reg h; wire i; wire j; + wire clk; initial d <= a; always @* begin @@ -62,6 +63,8 @@ module top; end end + always @(posedge clk); + assign b = g; endmodule |] @@ -74,6 +77,7 @@ module top; reg f; reg g; reg h; + wire clk; initial d <= a; always @* begin @@ -84,6 +88,8 @@ module top; end end + always @(posedge clk); + assign b = g; endmodule |] -- cgit From 11bd73faa516cde0af74e5359c36c8f1fa4e816a Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sat, 25 May 2019 23:26:27 +0100 Subject: Fix reduction for statements --- test/Reduce.hs | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) (limited to 'test') diff --git a/test/Reduce.hs b/test/Reduce.hs index bc4bbc3..be5ead3 100644 --- a/test/Reduce.hs +++ b/test/Reduce.hs @@ -29,6 +29,7 @@ reduceUnitTests = testGroup [ moduleReducerTest , modItemReduceTest , halveStatementsTest + , statementReducerTest , activeWireTest , cleanTest , cleanAllTest @@ -371,6 +372,94 @@ module top(y, x); endmodule |]) +-- brittany-disable-next-binding +statementReducerTest :: TestTree +statementReducerTest = testCase "Statement reducer" $ do + GenVerilog <$> halveStatements "top" srcInfo1 @?= fmap GenVerilog golden1 + GenVerilog <$> halveStatements "top" srcInfo2 @?= fmap GenVerilog golden2 + where + srcInfo1 = SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + a <= 1; + b <= 2; + c <= 3; + d <= 4; + end + + always @(posedge clk) begin + a <= 1; + b <= 2; + c <= 3; + d <= 4; + end +endmodule +|] + golden1 = Dual (SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + a <= 1; + b <= 2; + end + + always @(posedge clk) begin + a <= 1; + b <= 2; + end +endmodule +|]) $ SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + c <= 3; + d <= 4; + end + + always @(posedge clk) begin + c <= 3; + d <= 4; + end +endmodule +|] + srcInfo2 = SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) begin + if (x) + y <= 2; + else + y <= 3; + end +endmodule +|] + golden2 = Dual (SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) + y <= 2; +endmodule +|]) $ SourceInfo "top" [verilog| +module top(y, x); + output wire [4:0] y; + input wire [4:0] x; + + always @(posedge clk) + y <= 3; +endmodule +|] + -- brittany-disable-next-binding moduleReducerTest :: TestTree moduleReducerTest = testCase "Module reducer" $ do -- cgit From d32f4cc45bc8c0670fb788b1fcd4c2f2b15fa094 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sat, 29 Jun 2019 20:33:59 +0100 Subject: Format files --- test/Doctest.hs | 7 +++++-- test/Parser.hs | 13 +++++++++---- test/Property.hs | 27 +++++++++++++++++---------- test/Reduce.hs | 2 +- test/Unit.hs | 6 +++--- 5 files changed, 35 insertions(+), 20 deletions(-) (limited to 'test') diff --git a/test/Doctest.hs b/test/Doctest.hs index 7463dfe..9dc22a4 100644 --- a/test/Doctest.hs +++ b/test/Doctest.hs @@ -1,7 +1,10 @@ module Main where -import Build_doctests (flags, module_sources, pkgs) -import Test.DocTest (doctest) +import Build_doctests ( flags + , module_sources + , pkgs + ) +import Test.DocTest ( doctest ) main :: IO () main = doctest args where args = flags ++ pkgs ++ module_sources diff --git a/test/Parser.hs b/test/Parser.hs index 03cc3a6..84f1906 100644 --- a/test/Parser.hs +++ b/test/Parser.hs @@ -17,10 +17,15 @@ module Parser where import Control.Lens -import Data.Either (either, isRight) -import Hedgehog (Gen, Property, (===)) -import qualified Hedgehog as Hog -import qualified Hedgehog.Gen as Hog +import Data.Either ( either + , isRight + ) +import Hedgehog ( Gen + , Property + , (===) + ) +import qualified Hedgehog as Hog +import qualified Hedgehog.Gen as Hog import Test.Tasty import Test.Tasty.Hedgehog import Test.Tasty.HUnit diff --git a/test/Property.hs b/test/Property.hs index 001c7d3..4e17695 100644 --- a/test/Property.hs +++ b/test/Property.hs @@ -11,16 +11,23 @@ module Property ) where -import Data.Either (either, isRight) -import qualified Data.Graph.Inductive as G -import Data.Text (Text) -import Hedgehog (Gen, Property, (===)) -import qualified Hedgehog as Hog -import Hedgehog.Function (Arg, Vary) -import qualified Hedgehog.Function as Hog -import qualified Hedgehog.Gen as Hog -import qualified Hedgehog.Range as Hog -import Parser (parserTests) +import Data.Either ( either + , isRight + ) +import qualified Data.Graph.Inductive as G +import Data.Text ( Text ) +import Hedgehog ( Gen + , Property + , (===) + ) +import qualified Hedgehog as Hog +import Hedgehog.Function ( Arg + , Vary + ) +import qualified Hedgehog.Function as Hog +import qualified Hedgehog.Gen as Hog +import qualified Hedgehog.Range as Hog +import Parser ( parserTests ) import Test.Tasty import Test.Tasty.Hedgehog import Text.Parsec diff --git a/test/Reduce.hs b/test/Reduce.hs index be5ead3..bc47d94 100644 --- a/test/Reduce.hs +++ b/test/Reduce.hs @@ -17,7 +17,7 @@ module Reduce ) where -import Data.List ((\\)) +import Data.List ( (\\) ) import Test.Tasty import Test.Tasty.HUnit import VeriFuzz diff --git a/test/Unit.hs b/test/Unit.hs index 84508c4..aaffe09 100644 --- a/test/Unit.hs +++ b/test/Unit.hs @@ -4,9 +4,9 @@ module Unit where import Control.Lens -import Data.List.NonEmpty (NonEmpty (..)) -import Parser (parseUnitTests) -import Reduce (reduceUnitTests) +import Data.List.NonEmpty ( NonEmpty(..) ) +import Parser ( parseUnitTests ) +import Reduce ( reduceUnitTests ) import Test.Tasty import Test.Tasty.HUnit import VeriFuzz -- cgit