From 77702d5492ba19b6e3e0dda9e9460a8bb67a8e3f Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Thu, 9 May 2019 23:18:10 +0100
Subject: Add new pretty printer with indentation

---
 test/Doctest.hs  |  5 +----
 test/Property.hs | 29 +++--------------------------
 2 files changed, 4 insertions(+), 30 deletions(-)

(limited to 'test')

diff --git a/test/Doctest.hs b/test/Doctest.hs
index 44fecac..1b899c3 100644
--- a/test/Doctest.hs
+++ b/test/Doctest.hs
@@ -1,11 +1,8 @@
 module Main where
 
 import           Build_doctests (flags, module_sources, pkgs)
-import           Data.Foldable  (traverse_)
 import           Test.DocTest   (doctest)
 
 main :: IO ()
-main = do
-    traverse_ putStrLn args -- optionally print arguments
-    doctest args
+main = doctest args
     where args = flags ++ pkgs ++ module_sources
diff --git a/test/Property.hs b/test/Property.hs
index fe802c9..7b1771c 100644
--- a/test/Property.hs
+++ b/test/Property.hs
@@ -20,17 +20,15 @@ import           Hedgehog.Function       (Arg, Vary)
 import qualified Hedgehog.Function       as Hog
 import qualified Hedgehog.Gen            as Hog
 import qualified Hedgehog.Range          as Hog
+import           Parser                  (parserTests)
 import           Test.Tasty
 import           Test.Tasty.Hedgehog
 import           Text.Parsec
-import           VeriFuzz                hiding (Property)
+import           VeriFuzz
 import           VeriFuzz.Result
 import           VeriFuzz.Verilog.Lex
 import           VeriFuzz.Verilog.Parser
 
-randomMod' :: Gen ModDecl
-randomMod' = Hog.resize 20 (randomMod 3 10)
-
 randomDAG' :: Gen Circuit
 randomDAG' = Hog.resize 30 randomDAG
 
@@ -40,26 +38,6 @@ simpleGraph = Hog.property $ do
     Hog.assert $ simp xs
     where simp = G.isSimple . getCircuit
 
-parserInput :: Property
-parserInput = Hog.property $ do
-    v <- Hog.forAll randomMod'
-    Hog.assert . isRight $ parse parseModDecl
-                                 "input_test.v"
-                                 (alexScanTokens $ str v)
-    where str = show . GenVerilog
-
-parserIdempotent :: Property
-parserIdempotent = Hog.property $ do
-    v <- Hog.forAll randomMod'
-    let sv = vshow v
-    p sv === (p . p) sv
-  where
-    vshow = show . GenVerilog
-    p sv =
-        either (\x -> show x <> "\n" <> sv) vshow
-            . parse parseModDecl "idempotent_test.v"
-            $ alexScanTokens sv
-
 type GenFunctor f a b c =
     ( Functor f
     , Show (f a)
@@ -99,7 +77,6 @@ propertyTests :: TestTree
 propertyTests = testGroup
     "Property Tests"
     [ testProperty "simple graph generation check" simpleGraph
---    , testProperty "parser input"                  parserInput
---    , testProperty "parser idempotence"            parserIdempotent
     , testProperty "fmap for Result"               propertyResultInterrupted
+    , parserTests
     ]
-- 
cgit