From c3b5f3f5feeb2c7e9b807d96666603d52851b2e8 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Wed, 15 May 2019 00:55:16 +0100
Subject: Add test for removing unused wires

---
 test/Reduce.hs | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

(limited to 'test')

diff --git a/test/Reduce.hs b/test/Reduce.hs
index dd47f8b..9c59e48 100644
--- a/test/Reduce.hs
+++ b/test/Reduce.hs
@@ -32,8 +32,62 @@ reduceUnitTests = testGroup
     , activeWireTest
     , cleanTest
     , cleanAllTest
+    , removeDeclTest
     ]
 
+-- brittany-disable-next-binding
+removeDeclTest :: TestTree
+removeDeclTest = testCase "Remove declarations" $ do
+    GenVerilog (removeDecl srcInfo1) @?= golden1
+    where
+        srcInfo1 = SourceInfo "top" [verilog|
+module top;
+  wire a;
+  wire b;
+  wire c;
+  reg d;
+  reg e;
+  reg f;
+  reg g;
+  reg h;
+  wire i;
+  wire j;
+  initial d <= a;
+
+  always @* begin
+    f <= e;
+    g <= e;
+    if (1) begin
+      h <= h;
+    end
+  end
+
+  assign b = g;
+endmodule
+|]
+        golden1 = GenVerilog $ SourceInfo "top" [verilog|
+module top;
+  wire a;
+  wire b;
+  reg d;
+  reg e;
+  reg f;
+  reg g;
+  reg h;
+  initial d <= a;
+
+  always @* begin
+    f <= e;
+    g <= e;
+    if (1) begin
+      h <= h;
+    end
+  end
+
+  assign b = g;
+endmodule
+|]
+
 -- brittany-disable-next-binding
 cleanAllTest :: TestTree
 cleanAllTest = testCase "Clean all" $ do
-- 
cgit