From cccb665ebac6e916c4f961eacbe11a9af7d7ceb3 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 29 Aug 2019 15:44:33 +1000
Subject: Change name from VeriFuzz to VeriSmith

---
 test/Benchmark.hs |  2 +-
 test/Parser.hs    | 16 ++++++++--------
 test/Property.hs  | 35 ++++++++++++++---------------------
 test/Reduce.hs    |  4 ++--
 test/Unit.hs      |  8 ++++----
 5 files changed, 29 insertions(+), 36 deletions(-)

(limited to 'test')

diff --git a/test/Benchmark.hs b/test/Benchmark.hs
index d0ea9cd..7d59e2d 100644
--- a/test/Benchmark.hs
+++ b/test/Benchmark.hs
@@ -2,7 +2,7 @@ module Main where
 
 import           Control.Lens   ((&), (.~))
 import           Criterion.Main (bench, bgroup, defaultMain, nfAppIO)
-import           VeriFuzz       (configProperty, defaultConfig, proceduralIO,
+import           VeriSmith      (configProperty, defaultConfig, proceduralIO,
                                  propSize, propStmntDepth)
 
 main :: IO ()
diff --git a/test/Parser.hs b/test/Parser.hs
index d300d8a..b372bbe 100644
--- a/test/Parser.hs
+++ b/test/Parser.hs
@@ -17,18 +17,18 @@ module Parser
 where
 
 import           Control.Lens
-import           Data.Either             (either, isRight)
-import           Hedgehog                (Gen, Property, (===))
-import qualified Hedgehog                as Hog
-import qualified Hedgehog.Gen            as Hog
+import           Data.Either              (either, isRight)
+import           Hedgehog                 (Gen, Property, (===))
+import qualified Hedgehog                 as Hog
+import qualified Hedgehog.Gen             as Hog
 import           Test.Tasty
 import           Test.Tasty.Hedgehog
 import           Test.Tasty.HUnit
 import           Text.Parsec
-import           VeriFuzz
-import           VeriFuzz.Internal
-import           VeriFuzz.Verilog.Lex
-import           VeriFuzz.Verilog.Parser
+import           VeriSmith
+import           VeriSmith.Internal
+import           VeriSmith.Verilog.Lex
+import           VeriSmith.Verilog.Parser
 
 smallConfig :: Config
 smallConfig = defaultConfig & configProperty . propSize .~ 5
diff --git a/test/Property.hs b/test/Property.hs
index 4e17695..afb1d11 100644
--- a/test/Property.hs
+++ b/test/Property.hs
@@ -11,30 +11,23 @@ module Property
     )
 where
 
-import           Data.Either                    ( either
-                                                , isRight
-                                                )
-import qualified Data.Graph.Inductive          as G
-import           Data.Text                      ( Text )
-import           Hedgehog                       ( Gen
-                                                , Property
-                                                , (===)
-                                                )
-import qualified Hedgehog                      as Hog
-import           Hedgehog.Function              ( Arg
-                                                , Vary
-                                                )
-import qualified Hedgehog.Function             as Hog
-import qualified Hedgehog.Gen                  as Hog
-import qualified Hedgehog.Range                as Hog
-import           Parser                         ( parserTests )
+import           Data.Either              (either, isRight)
+import qualified Data.Graph.Inductive     as G
+import           Data.Text                (Text)
+import           Hedgehog                 (Gen, Property, (===))
+import qualified Hedgehog                 as Hog
+import           Hedgehog.Function        (Arg, Vary)
+import qualified Hedgehog.Function        as Hog
+import qualified Hedgehog.Gen             as Hog
+import qualified Hedgehog.Range           as Hog
+import           Parser                   (parserTests)
 import           Test.Tasty
 import           Test.Tasty.Hedgehog
 import           Text.Parsec
-import           VeriFuzz
-import           VeriFuzz.Result
-import           VeriFuzz.Verilog.Lex
-import           VeriFuzz.Verilog.Parser
+import           VeriSmith
+import           VeriSmith.Result
+import           VeriSmith.Verilog.Lex
+import           VeriSmith.Verilog.Parser
 
 randomDAG' :: Gen Circuit
 randomDAG' = Hog.resize 30 randomDAG
diff --git a/test/Reduce.hs b/test/Reduce.hs
index 722ddea..f3ddf5c 100644
--- a/test/Reduce.hs
+++ b/test/Reduce.hs
@@ -20,8 +20,8 @@ where
 import           Data.List        ((\\))
 import           Test.Tasty
 import           Test.Tasty.HUnit
-import           VeriFuzz
-import           VeriFuzz.Reduce
+import           VeriSmith
+import           VeriSmith.Reduce
 
 reduceUnitTests :: TestTree
 reduceUnitTests = testGroup
diff --git a/test/Unit.hs b/test/Unit.hs
index aaffe09..f9283be 100644
--- a/test/Unit.hs
+++ b/test/Unit.hs
@@ -4,12 +4,12 @@ module Unit
 where
 
 import           Control.Lens
-import           Data.List.NonEmpty             ( NonEmpty(..) )
-import           Parser                         ( parseUnitTests )
-import           Reduce                         ( reduceUnitTests )
+import           Data.List.NonEmpty (NonEmpty (..))
+import           Parser             (parseUnitTests)
+import           Reduce             (reduceUnitTests)
 import           Test.Tasty
 import           Test.Tasty.HUnit
-import           VeriFuzz
+import           VeriSmith
 
 unitTests :: TestTree
 unitTests = testGroup
-- 
cgit