From e7f7d1988ad9a161ba10e36859dc04a92422a4e0 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Wed, 7 Nov 2018 14:44:39 +0000 Subject: Add simple verilog AND gate --- test/simple.v | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 test/simple.v (limited to 'test') diff --git a/test/simple.v b/test/simple.v new file mode 100644 index 0000000..5198d3d --- /dev/null +++ b/test/simple.v @@ -0,0 +1,23 @@ +module and_comb(in1, in2, out); + input in1; + input in2; + output out; + + assign out = in1 & in2; +endmodule + +module main; + reg a, b; + wire c; + + and_comb gate(.in1(a), .in2(b), .out(c)); + + initial + begin + a = 1'b1; + b = 1'b1; + #1 + $display("%d & %d = %d", a, b, c); + $finish; + end +endmodule -- cgit