From f3c1942b50bfc294cbede8ae502b5f6cb306da7e Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@ymhg.org>
Date: Sun, 12 May 2019 00:14:15 +0100
Subject: Add working statement reduction

---
 test/Reduce.hs | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)

(limited to 'test')

diff --git a/test/Reduce.hs b/test/Reduce.hs
index 5afae18..37a2604 100644
--- a/test/Reduce.hs
+++ b/test/Reduce.hs
@@ -26,6 +26,7 @@ reduceUnitTests :: TestTree
 reduceUnitTests = testGroup "Reducer tests"
     [ moduleReducerTest
     , modItemReduceTest
+    , halveStatementsTest
     , activeWireTest
     ]
 
@@ -33,6 +34,7 @@ activeWireTest :: TestTree
 activeWireTest = testCase "Active wires" $ do
     findActiveWires verilog1 \\ ["x", "y", "z", "w"] @?= []
     findActiveWires verilog2 \\ ["x", "y", "z"] @?= []
+    findActiveWires verilog3 \\ ["x", "y", "clk", "r1", "r2"] @?= []
     where
         verilog1 = head $ getVerilog [verilog|
 module top(y, x);
@@ -54,6 +56,89 @@ module top(y, x);
   assign z = 0;
 endmodule
 |]
+        verilog3 = head $ getVerilog [verilog|
+module top(clk, y, x);
+  input clk;
+  input x;
+  output y;
+  reg r1;
+  reg r2;
+  reg r3;
+  always @(posedge clk) begin
+    r1 <= r3;
+    r2 <= r1;
+  end
+
+  always @(posedge clk) begin
+    r1 <= r2;
+  end
+  assign y = {r1, r2, r3};
+endmodule
+|]
+
+halveStatementsTest :: TestTree
+halveStatementsTest = testCase "Statements" $ do
+    GenVerilog <$> halveStatements srcInfo1 @?= golden1
+    where
+        srcInfo1 = SourceInfo "top" [verilog|
+module top(clk, y, x);
+  input clk;
+  input x;
+  output y;
+  reg r1;
+  reg r2;
+  reg r3;
+  always @(posedge clk) begin
+    r1 <= r3;
+    r2 <= r1;
+    r3 <= r2;
+  end
+
+  always @(posedge clk) begin
+    r1 <= r2;
+    r2 <= r3;
+    r3 <= r1;
+  end
+  assign y = {r1, r2, r3};
+endmodule
+|]
+        golden1 = GenVerilog <$> Dual (SourceInfo "top" [verilog|
+module top(clk, y, x);
+  input clk;
+  input x;
+  output y;
+  reg r1;
+  reg r2;
+  reg r3;
+  always @(posedge clk) begin
+    r1 <= 1'b0;
+  end
+
+  always @(posedge clk) begin
+    r1 <= 1'b0;
+  end
+  assign y = {r1, 1'b0, 1'b0};
+endmodule
+|]) (SourceInfo "top" [verilog|
+module top(clk, y, x);
+  input clk;
+  input x;
+  output y;
+  reg r1;
+  reg r2;
+  reg r3;
+  always @(posedge clk) begin
+    r2 <= 1'b0;
+    r3 <= r2;
+  end
+
+  always @(posedge clk) begin
+    r2 <= r3;
+    r3 <= 1'b0;
+  end
+  assign y = {1'b0, r2, r3};
+endmodule
+|])
 
 modItemReduceTest :: TestTree
 modItemReduceTest = testCase "Module items" $ do
-- 
cgit