From 4ce63111a9cc7b82d713e1f61f30dcc1a39a71ad Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Sat, 29 Dec 2018 22:30:11 +0100
Subject: Add tests for new generation method

---
 tests/Unit.hs | 9 ---------
 1 file changed, 9 deletions(-)

(limited to 'tests/Unit.hs')

diff --git a/tests/Unit.hs b/tests/Unit.hs
index 67f642c..de4fa16 100644
--- a/tests/Unit.hs
+++ b/tests/Unit.hs
@@ -38,12 +38,3 @@ trans e =
                               PrimExpr . PrimId $ Identifier "Replaced"
                             else PrimExpr (PrimId id)
     _                    -> e
-
-runMain = do
-  gr <- genRandomDAG 100 :: IO (G.Gr Gate ())
---  _ <- runGraphviz (graphToDot quickParams $ emap (const "") gr) Png "output.png",
---  T.putStrLn $ generate gr
-  --g <- QC.generate (QC.arbitrary :: QC.Gen VerilogSrc)
-  let x = generateAST $ Circuit gr
-  let y = head . reverse $ x ^.. getVerilogSrc . traverse . getDescription . moduleItems . traverse . _ModCA . contAssignExpr
-  print $ transformOf traverseExpr trans y
-- 
cgit