# Synthesis issue with shift and multiplication

[ Fixed in [`349c472`](https://github.com/YosysHQ/yosys/commit/349c47250a9779bc58634870d2e3facfe95fbff8) | [Issue 1047](https://github.com/YosysHQ/yosys/issues/1047) ]

## Affected versions

- Yosys 0.8+498

## Description

### Steps to reproduce the issue

Consider the following Verilog code

```verilog
module top (y, w);
   output y;
   input [2:0] w;
   assign y = 1'b1 >> (w * (3'b110));
endmodule
```

Run with yosys version

```text
Generated by Yosys 0.8+498 (git sha1 92dde319, clang 8.0.0 -fPIC -Os)
```

and the following command

```text
yosys -p 'read -formal rtl.v; synth; write_verilog -noattr syn_yosys.v'
```

### Expected behavior

When passing the input `3'b100`, I would expect the output to give `1'b1`, as `3'b100 * 3'b110 = 3'b000`.

### Actual behavior

The synthesised output is the following, which when given `3'b100` gives `1'b0` as output.

```verilog
module top(y, w);
  wire _0_;
  input [2:0] w;
  output y;
  assign _0_ = ~(w[1] | w[0]);
  assign y = _0_ & ~(w[2]);
endmodule
```

I have included a testbench with iverilog and SymbiYosys script that compares the RTL to the synthesised Verilog. To run everything, run `./run.sh`.

[test_bug.zip](https://github.com/YosysHQ/yosys/files/3227136/test_bug.zip)