+++
title = "Global State"
author = "Yann Herklotz"
tags = []
categories = []
backlinks = ["1b4"]
forwardlinks = ["1b6"]
zettelid = "1b5"
+++

It is quite tricky to synthesise global state, as global variables are
not a thing in Verilog. There are therefore two alternatives, either all
the global variables have to be passed to all the modules, or memory has
to be used to store the global state and it then has to be retrieved.
However, to start out, if only one module is generated, and if module
instantiations are never used, then global variables can just be
supported by defining them in the main module.