+++ title = "Soft scheduling" author = "Yann Herklotz" tags = [] categories = [] backlinks = ["1c2f"] forwardlinks = ["1c2", "1c5", "1c2e", "1c2h"] zettelid = "1c2g" +++ Soft scheduling \[1\] is when scheduling optimisations are performed before the actual scheduling, to be able to better schedule the code. These can include register pressure optimisations such as shown in Beidas et al. \[1\], which can improve scheduling ([\#1c2]) and register allocation ([\#1c5]) but also maybe modulo scheduling ([\#1c2e]) without having to really place the instructions into proper clock cycles. This is contrary to how normal HLS tools perform their optimisations, because they normally do the scheduling in one step, so that all the information is available at once. However, I do not think that this works that well, because with too much information one has to analyse too much to be able to effectively perform each optimisation correctly. Instead, if each pass is separated, they can also be improved separately, instead of having to change one large scheduling algorithm. However, SDC Scheduling \[2\] does seem to be an interesting idea as it provides a general framework to express constraints in.
\[1\] R. Beidas, W. S. Mong, and J. Zhu, “Register pressure aware scheduling for high level synthesis,” in *16th asia and south pacific design automation conference (ASP-DAC 2011)*, Jan. 2011, pp. 461–466. doi: [10.1109/ASPDAC.2011.5722234].
\[2\] J. Cong and Z. Zhang, “An efficient and versatile scheduling algorithm based on SDC formulation,” in *2006 43rd ACM/IEEE design automation conference*, Jul. 2006, pp. 433–438. doi: [10.1145/1146909.1147025].
[\#1c2]: /zettel/1c2 [\#1c5]: /zettel/1c5 [\#1c2e]: /zettel/1c2e [10.1109/ASPDAC.2011.5722234]: https://doi.org/10.1109/ASPDAC.2011.5722234 [10.1145/1146909.1147025]: https://doi.org/10.1145/1146909.1147025