+++
title = "Combining Loop Pipelining and Scheduling "
author = "Yann Herklotz"
tags = []
categories = []
backlinks = ["3c", "1c6"]
forwardlinks = ["1c6", "1c6a", "3c2"]
zettelid = "3c1"
+++

A [high-level synthesis] tool needs to perform various optimisations to.

The idea is to simulate full resource constrained scheduling with loop
pipelining ([\#1c6]) by splitting up the transformation into two steps.
One thing to consider is that this is software loop scheduling
([\#1c6a]).

1.  First, resource constrained iterative modulo scheduling \[1\] can be
    performed, which only affects loops and schedules each instruction
    into a clock cycle. This can move instructions over loop boundaries
    to create a more compact schedule and pipeline the instructions.
2.  Second, resource constrained scheduling can be performed on all the
    instructions in the program, by limiting each schedule to a basic
    block at a time. This will parallelise the epilogue that was
    generated in the iterative modulo scheduling step.

<div id="refs" class="references csl-bib-body" markdown="1">

<div id="ref-rau96_iterat_modul_sched" class="csl-entry" markdown="1">

<span class="csl-left-margin">\[1\]
</span><span class="csl-right-inline">B. R. Rau, “Iterative modulo
scheduling,” *International Journal of Parallel Programming*, vol. 24,
no. 1, pp. 3–64, Feb. 1996, Available:
<https://doi.org/10.1007/BF03356742></span>

</div>

</div>

  [high-level synthesis]: hls.org
  [\#1c6]: /zettel/1c6
  [\#1c6a]: /zettel/1c6a