+++
title = "Travelling CE"
author = "Yann Herklotz"
tags = []
categories = []
backlinks = ["5a2a"]
forwardlinks = ["5a2c"]
zettelid = "5a2b"
+++

One solution to the requirement of constant rate of the input data, is
to have a travelling enable signal that sets each stage to be true
sequentially. This can be formulated as the following:

``` verilog
initial o_ce = 1'b0;
always @(posedge i_clk)
  if (i_reset)
    o_ce <= 1'b0;
  else
    o_ce <= i_ce;
always @(posedge i_clk)
  if (i_ce)
    o_output <= $func(i_input);
```