# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 15:28:35  February 19, 2016
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		registered_multiply_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C16F484C6
set_global_assignment -name TOP_LEVEL_ENTITY registered_multiply
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:28:35  FEBRUARY 19, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name BDF_FILE ../ten_bit_adder_NO_BUS/ten_bit_adder_NO_BUS.bdf
set_global_assignment -name BDF_FILE ../adder/full_adder.bdf
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name BDF_FILE ../comb_multiply/registered_multiply.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_G5 -to A[4]
set_location_assignment PIN_G4 -to A[3]
set_location_assignment PIN_H6 -to A[2]
set_location_assignment PIN_H5 -to A[1]
set_location_assignment PIN_J6 -to A[0]
set_location_assignment PIN_D2 -to B[4]
set_location_assignment PIN_E4 -to B[3]
set_location_assignment PIN_E3 -to B[2]
set_location_assignment PIN_H7 -to B[1]
set_location_assignment PIN_J7 -to B[0]
set_location_assignment PIN_F1 -to CLK
set_location_assignment PIN_B1 -to Output[9]
set_location_assignment PIN_B2 -to Output[8]
set_location_assignment PIN_C2 -to Output[7]
set_location_assignment PIN_C1 -to Output[6]
set_location_assignment PIN_E1 -to Output[5]
set_location_assignment PIN_F2 -to Output[4]
set_location_assignment PIN_H1 -to Output[3]
set_location_assignment PIN_J3 -to Output[2]
set_location_assignment PIN_J2 -to Output[1]
set_location_assignment PIN_J1 -to Output[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name CDF_FILE output_files/Chain3.cdf