From 557fd604e7c9a079d136c76089446d9c714438ec Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Sun, 19 Feb 2017 23:17:47 +0000 Subject: Adding initial files --- FPGA-led-lights.gise | 28 ++++ FPGA-led-lights.xise | 385 +++++++++++++++++++++++++++++++++++++++++++++++++ _xmsgs/pn_parser.xmsgs | 15 ++ _xmsgs/xst.xmsgs | 12 ++ iseconfig/led.xreport | 215 +++++++++++++++++++++++++++ led.cmd_log | 1 + led.lso | 1 + led.prj | 1 + led.syr | 128 ++++++++++++++++ led.v | 25 ++++ led.xst | 56 +++++++ led_envsettings.html | 382 ++++++++++++++++++++++++++++++++++++++++++++++++ led_summary.html | 84 +++++++++++ led_xst.xrpt | 115 +++++++++++++++ webtalk_pn.xml | 42 ++++++ xst/work/hdllib.ref | 1 + xst/work/vlg69/led.bin | Bin 0 -> 271 bytes 17 files changed, 1491 insertions(+) create mode 100644 FPGA-led-lights.gise create mode 100644 FPGA-led-lights.xise create mode 100644 _xmsgs/pn_parser.xmsgs create mode 100644 _xmsgs/xst.xmsgs create mode 100644 iseconfig/led.xreport create mode 100644 led.cmd_log create mode 100644 led.lso create mode 100644 led.prj create mode 100644 led.syr create mode 100644 led.v create mode 100644 led.xst create mode 100644 led_envsettings.html create mode 100644 led_summary.html create mode 100644 led_xst.xrpt create mode 100644 webtalk_pn.xml create mode 100644 xst/work/hdllib.ref create mode 100644 xst/work/vlg69/led.bin diff --git a/FPGA-led-lights.gise b/FPGA-led-lights.gise new file mode 100644 index 0000000..206faba --- /dev/null +++ b/FPGA-led-lights.gise @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + diff --git a/FPGA-led-lights.xise b/FPGA-led-lights.xise new file mode 100644 index 0000000..9bde54a --- /dev/null +++ b/FPGA-led-lights.xise @@ -0,0 +1,385 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..ffaa88d --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ + + + + + + + + + + +Analyzing Verilog file "/home/yannherklotz/Github/FPGA-led-lights/led.v" into library work + + + + diff --git a/_xmsgs/xst.xmsgs b/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..e32e993 --- /dev/null +++ b/_xmsgs/xst.xmsgs @@ -0,0 +1,12 @@ + + + +"led.v" line 21: Module <led> has no port. + + + + diff --git a/iseconfig/led.xreport b/iseconfig/led.xreport new file mode 100644 index 0000000..8f92663 --- /dev/null +++ b/iseconfig/led.xreport @@ -0,0 +1,215 @@ + + +
+ 2017-02-19T23:10:42 + led + Unknown + /home/yannherklotz/Github/FPGA-led-lights/iseconfig/led.xreport + /home/yannherklotz/Github/FPGA-led-lights + 2017-02-19T23:10:42 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/led.cmd_log b/led.cmd_log new file mode 100644 index 0000000..1e860a3 --- /dev/null +++ b/led.cmd_log @@ -0,0 +1 @@ +xst -intstyle ise -ifn "/home/yannherklotz/Github/FPGA-led-lights/led.xst" -ofn "/home/yannherklotz/Github/FPGA-led-lights/led.syr" diff --git a/led.lso b/led.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/led.lso @@ -0,0 +1 @@ +work diff --git a/led.prj b/led.prj new file mode 100644 index 0000000..1a2acfa --- /dev/null +++ b/led.prj @@ -0,0 +1 @@ +verilog work "led.v" diff --git a/led.syr b/led.syr new file mode 100644 index 0000000..5e4ba5c --- /dev/null +++ b/led.syr @@ -0,0 +1,128 @@ +Release 14.7 - xst P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> +Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.03 secs + +--> +Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.03 secs + +--> +Reading design: led.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) Partition Resource Summary + 9.3) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "led.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "led" +Output Format : NGC +Target Device : xc3s250e-4-vq100 + +---- Source Options +Top Module Name : led +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : Yes +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +ROM Style : Auto +Mux Extraction : Yes +Resource Sharing : YES +Asynchronous To Synchronous : NO +Multiplier Style : Auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 24 +Register Duplication : YES +Slice Packing : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Yes +Use Synchronous Set : Yes +Use Synchronous Reset : Yes +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +Verilog 2001 : YES +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling verilog file "led.v" in library work +Module compiled +No errors in compilation +Analysis of file <"led.prj"> succeeded. + + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +ERROR:Xst - "led.v" line 21: Module has no port. +--> + + +Total memory usage is 497212 kilobytes + +Number of errors : 1 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + diff --git a/led.v b/led.v new file mode 100644 index 0000000..28d6363 --- /dev/null +++ b/led.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: Yann Herklotz +// +// Create Date: 23:10:42 02/19/2017 +// Design Name: +// Module Name: led +// Project Name: +// Target Devices: Papilio Pro +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module led( + ); + + +endmodule diff --git a/led.xst b/led.xst new file mode 100644 index 0000000..0a62f03 --- /dev/null +++ b/led.xst @@ -0,0 +1,56 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn led.prj +-ifmt mixed +-ofn led +-ofmt NGC +-p xc3s250e-4-vq100 +-top led +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-mult_style Auto +-iobuf YES +-max_fanout 500 +-bufg 24 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/led_envsettings.html b/led_envsettings.html new file mode 100644 index 0000000..215f634 --- /dev/null +++ b/led_envsettings.html @@ -0,0 +1,382 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
LD_LIBRARY_PATH/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/common/lib/lin64		< data not available >< data not available >< data not available >
PATH/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:
/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:
/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:
/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:
/usr/local/sbin:
/usr/local/bin:
/usr/bin:
/usr/lib/jvm/default/bin:
/usr/bin/site_perl:
/usr/bin/vendor_perl:
/usr/bin/core_perl		< data not available >< data not available >< data not available >
XILINX/opt/Xilinx/14.7/ISE_DS/ISE/< data not available >< data not available >< data not available >
XILINX_DSP/opt/Xilinx/14.7/ISE_DS/ISE< data not available >< data not available >< data not available >
XILINX_EDK/opt/Xilinx/14.7/ISE_DS/EDK< data not available >< data not available >< data not available >
XILINX_PLANAHEAD/opt/Xilinx/14.7/ISE_DS/PlanAhead< data not available >< data not available >< data not available >
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn led.prj 
-ifmt mixedMIXED
-ofn led 
-ofmt NGCNGC
-p xc3s250e-4-vq100 
-top led 
-opt_modeOptimization GoalSpeedSPEED
-opt_levelOptimization Effort11
-iucUse synthesis Constraints FileNONO
-keep_hierarchyKeep HierarchyNoNO
-netlist_hierarchyNetlist HierarchyAs_Optimizedas_optimized
-rtlviewGenerate RTL SchematicYesNO
-glob_optGlobal Optimization GoalAllClockNetsALLCLOCKNETS
-read_coresRead CoresYESYES
-write_timing_constraintsWrite Timing ConstraintsNONO
-cross_clock_analysisCross Clock AnalysisNONO
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100%
-bram_utilization_ratioBRAM Utilization Ratio100100%
-verilog2001Verilog 2001YESYES
-fsm_extract YESYES
-fsm_encoding AutoAUTO
-safe_implementation NoNO
-fsm_style LUTLUT
-ram_extract YesYES
-ram_style AutoAUTO
-rom_extract YesYES
-shreg_extract YESYES
-rom_style AutoAUTO
-auto_bram_packing NONO
-resource_sharing YESYES
-async_to_sync NONO
-mult_style AutoAUTO
-iobuf YESYES
-max_fanout 500500
-bufg 2424
-register_duplication YESYES
-register_balancing NoNO
-optimize_primitives NONO
-use_clock_enable YesYES
-use_sync_set YesYES
-use_sync_reset YesYES
-iob AutoAUTO
-equivalent_register_removal YESYES
-slice_utilization_ratio_maxmargin 50%
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i5-7200U CPU @ 2.50GHz/3099.957 MHz<  data not available  ><  data not available  ><  data not available  >
Hostyann-arch<  data not available  ><  data not available  ><  data not available  >
OS Nameunknown<  data not available  ><  data not available  ><  data not available  >
OS Releaseunknown<  data not available  ><  data not available  ><  data not available  >
+ \ No newline at end of file diff --git a/led_summary.html b/led_summary.html new file mode 100644 index 0000000..4cea820 --- /dev/null +++ b/led_summary.html @@ -0,0 +1,84 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
led Project Status (02/19/2017 - 23:15:32)
Project File:FPGA-led-lights.xiseParser Errors: No Errors
Module Name:ledImplementation State:Synthesized (Failed)
Target Device:xc3s250e-4vq100
  • Errors:
 +X +1 Error (1 new)
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: + +System Settings +
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentSun Feb 19 23:15:32 2017X 1 Error (1 new)00
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 02/19/2017 - 23:15:49
+ \ No newline at end of file diff --git a/led_xst.xrpt b/led_xst.xrpt new file mode 100644 index 0000000..799a43f --- /dev/null +++ b/led_xst.xrpt @@ -0,0 +1,115 @@ + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + +
+ + + diff --git a/webtalk_pn.xml b/webtalk_pn.xml new file mode 100644 index 0000000..e745db1 --- /dev/null +++ b/webtalk_pn.xml @@ -0,0 +1,42 @@ + + + + +
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/xst/work/hdllib.ref b/xst/work/hdllib.ref new file mode 100644 index 0000000..a3fd458 --- /dev/null +++ b/xst/work/hdllib.ref @@ -0,0 +1 @@ +MO led NULL led.v vlg69/led.bin 1487546132 diff --git a/xst/work/vlg69/led.bin b/xst/work/vlg69/led.bin new file mode 100644 index 0000000..5060a66 Binary files /dev/null and b/xst/work/vlg69/led.bin differ -- cgit