Release 14.7 - xst P.20131013 (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.02 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.03 secs --> Reading design: led.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "led.prj" Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "led" Output Format : NGC Target Device : xc6slx9-2-tqg144 ---- Source Options Top Module Name : led Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Shift Register Extraction : YES ROM Style : Auto Resource Sharing : YES Asynchronous To Synchronous : NO Shift Register Minimum Size : 2 Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options LUT Combining : Auto Reduce Control Sets : Auto Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Parsing * ========================================================================= Analyzing Verilog file "/home/yannherklotz/Github/FPGA-led-lights/led.v" into library work Parsing module . ========================================================================= * HDL Elaboration * ========================================================================= Elaborating module . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "/home/yannherklotz/Github/FPGA-led-lights/led.v". Found 27-bit register for signal . Found 1-bit register for signal . Found 27-bit subtractor for signal created at line 41. Summary: inferred 1 Adder/Subtractor(s). inferred 28 D-type flip-flop(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 27-bit subtractor : 1 # Registers : 2 1-bit register : 1 27-bit register : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Synthesizing (advanced) Unit . The following registers are absorbed into counter : 1 register on signal . Unit synthesized (advanced). ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Counters : 1 27-bit down counter : 1 # Registers : 1 Flip-Flops : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block led, actual ratio is 0. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 25 Flip-Flops : 25 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Design Summary * ========================================================================= Top Level Output File Name : led.ngc Primitive and Black Box Usage: ------------------------------ # BELS : 106 # GND : 1 # INV : 23 # LUT1 : 1 # LUT5 : 25 # LUT6 : 8 # MUXCY : 23 # VCC : 1 # XORCY : 24 # FlipFlops/Latches : 25 # FD : 25 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 1 # OBUF : 1 Device utilization summary: --------------------------- Selected Device : 6slx9tqg144-2 Slice Logic Utilization: Number of Slice Registers: 25 out of 11440 0% Number of Slice LUTs: 57 out of 5720 0% Number used as Logic: 57 out of 5720 0% Slice Logic Distribution: Number of LUT Flip Flop pairs used: 57 Number with an unused Flip Flop: 32 out of 57 56% Number with an unused LUT: 0 out of 57 0% Number of fully used LUT-FF pairs: 25 out of 57 43% Number of unique control sets: 1 IO Utilization: Number of IOs: 2 Number of bonded IOBs: 2 out of 102 1% Specific Feature Utilization: Number of BUFG/BUFGCTRLs: 1 out of 16 6% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= Timing Report NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ CLK | BUFGP | 25 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -2 Minimum period: 3.825ns (Maximum Frequency: 261.472MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 4.162ns Maximum combinational path delay: No path found Timing Details: --------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'CLK' Clock period: 3.825ns (frequency: 261.472MHz) Total number of paths / destination ports: 901 / 25 ------------------------------------------------------------------------- Delay: 3.825ns (Levels of Logic = 22) Source: count_0 (FF) Destination: count_19 (FF) Source Clock: CLK rising Destination Clock: CLK rising Data Path: count_0 to count_19 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 3 0.525 0.766 count_0 (count_0) LUT1:I0->O 1 0.254 0.000 Mcount_count_cy<0>_rt (Mcount_count_cy<0>_rt) MUXCY:S->O 1 0.215 0.000 Mcount_count_cy<0> (Mcount_count_cy<0>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<1> (Mcount_count_cy<1>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<2> (Mcount_count_cy<2>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<3> (Mcount_count_cy<3>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<4> (Mcount_count_cy<4>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<5> (Mcount_count_cy<5>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<6> (Mcount_count_cy<6>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<7> (Mcount_count_cy<7>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<8> (Mcount_count_cy<8>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<9> (Mcount_count_cy<9>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<10> (Mcount_count_cy<10>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<11> (Mcount_count_cy<11>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<12> (Mcount_count_cy<12>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<13> (Mcount_count_cy<13>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<14> (Mcount_count_cy<14>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<15> (Mcount_count_cy<15>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<16> (Mcount_count_cy<16>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<17> (Mcount_count_cy<17>) MUXCY:CI->O 1 0.023 0.000 Mcount_count_cy<18> (Mcount_count_cy<18>) XORCY:CI->O 1 0.206 1.112 Mcount_count_xor<19> (Result<19>) LUT5:I0->O 1 0.254 0.000 count_19_rstpot (count_19_rstpot) FD:D 0.074 count_19 ---------------------------------------- Total 3.825ns (1.947ns logic, 1.878ns route) (50.9% logic, 49.1% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK' Total number of paths / destination ports: 1 / 1 ------------------------------------------------------------------------- Offset: 4.162ns (Levels of Logic = 1) Source: LED1 (FF) Destination: LED1 (PAD) Source Clock: CLK rising Data Path: LED1 to LED1 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 2 0.525 0.725 LED1 (LED1_OBUF) OBUF:I->O 2.912 LED1_OBUF (LED1) ---------------------------------------- Total 4.162ns (3.437ns logic, 0.725ns route) (82.6% logic, 17.4% route) ========================================================================= Cross Clock Domains Report: -------------------------- Clock to Setup on destination clock CLK ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ CLK | 3.825| | | | ---------------+---------+---------+---------+---------+ ========================================================================= Total REAL time to Xst completion: 4.00 secs Total CPU time to Xst completion: 4.11 secs --> Total memory usage is 382892 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 3 ( 0 filtered) Number of infos : 0 ( 0 filtered)