-------------------------------------------------------------------------------- Release 14.7 Trace (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml led.twx led.ncd -o led.twr led.pcf -ucf BPC3011-Papilio_Pro-general.ucf Design file: led.ncd Physical constraint file: led.pcf Device,package,speed: xc6slx9,tqg144,C,-2 (PRODUCTION 1.23 2013-10-13) Report level: verbose report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. ================================================================================ Timing constraint: NET "CLK_BUFGP/IBUFG" PERIOD = 31.25 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 901 paths analyzed, 125 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 3.695ns. -------------------------------------------------------------------------------- Paths for end point count_1 (SLICE_X13Y38.B1), 6 paths -------------------------------------------------------------------------------- Slack (setup path): 27.555ns (requirement - (data path - clock path skew + uncertainty)) Source: count_9 (FF) Destination: count_1 (FF) Requirement: 31.250ns Data Path Delay: 3.645ns (Levels of Logic = 2) Clock Path Skew: -0.015ns (0.285 - 0.300) Source Clock: CLK_BUFGP rising at 0.000ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: count_9 to count_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y40.BQ Tcko 0.430 count<11> count_9 SLICE_X14Y41.B3 net (fanout=3) 1.341 count<9> SLICE_X14Y41.B Tilo 0.235 LED1_OBUF count[26]_GND_1_o_equal_2_o<26>4 SLICE_X13Y38.B1 net (fanout=19) 1.266 count[26]_GND_1_o_equal_2_o<26>3 SLICE_X13Y38.CLK Tas 0.373 count<3> count_1_rstpot count_1 ------------------------------------------------- --------------------------- Total 3.645ns (1.038ns logic, 2.607ns route) (28.5% logic, 71.5% route) -------------------------------------------------------------------------------- Slack (setup path): 27.760ns (requirement - (data path - clock path skew + uncertainty)) Source: count_10 (FF) Destination: count_1 (FF) Requirement: 31.250ns Data Path Delay: 3.440ns (Levels of Logic = 2) Clock Path Skew: -0.015ns (0.285 - 0.300) Source Clock: CLK_BUFGP rising at 0.000ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: count_10 to count_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y40.CQ Tcko 0.430 count<11> count_10 SLICE_X14Y41.B1 net (fanout=3) 1.136 count<10> SLICE_X14Y41.B Tilo 0.235 LED1_OBUF count[26]_GND_1_o_equal_2_o<26>4 SLICE_X13Y38.B1 net (fanout=19) 1.266 count[26]_GND_1_o_equal_2_o<26>3 SLICE_X13Y38.CLK Tas 0.373 count<3> count_1_rstpot count_1 ------------------------------------------------- --------------------------- Total 3.440ns (1.038ns logic, 2.402ns route) (30.2% logic, 69.8% route) -------------------------------------------------------------------------------- Slack (setup path): 27.948ns (requirement - (data path - clock path skew + uncertainty)) Source: count_11 (FF) Destination: count_1 (FF) Requirement: 31.250ns Data Path Delay: 3.252ns (Levels of Logic = 2) Clock Path Skew: -0.015ns (0.285 - 0.300) Source Clock: CLK_BUFGP rising at 0.000ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: count_11 to count_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y40.DQ Tcko 0.430 count<11> count_11 SLICE_X14Y41.B2 net (fanout=3) 0.948 count<11> SLICE_X14Y41.B Tilo 0.235 LED1_OBUF count[26]_GND_1_o_equal_2_o<26>4 SLICE_X13Y38.B1 net (fanout=19) 1.266 count[26]_GND_1_o_equal_2_o<26>3 SLICE_X13Y38.CLK Tas 0.373 count<3> count_1_rstpot count_1 ------------------------------------------------- --------------------------- Total 3.252ns (1.038ns logic, 2.214ns route) (31.9% logic, 68.1% route) -------------------------------------------------------------------------------- Paths for end point count_7 (SLICE_X13Y39.D2), 6 paths -------------------------------------------------------------------------------- Slack (setup path): 27.560ns (requirement - (data path - clock path skew + uncertainty)) Source: count_9 (FF) Destination: count_7 (FF) Requirement: 31.250ns Data Path Delay: 3.638ns (Levels of Logic = 2) Clock Path Skew: -0.017ns (0.283 - 0.300) Source Clock: CLK_BUFGP rising at 0.000ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: count_9 to count_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y40.BQ Tcko 0.430 count<11> count_9 SLICE_X14Y41.B3 net (fanout=3) 1.341 count<9> SLICE_X14Y41.B Tilo 0.235 LED1_OBUF count[26]_GND_1_o_equal_2_o<26>4 SLICE_X13Y39.D2 net (fanout=19) 1.259 count[26]_GND_1_o_equal_2_o<26>3 SLICE_X13Y39.CLK Tas 0.373 count<7> count_7_rstpot count_7 ------------------------------------------------- --------------------------- Total 3.638ns (1.038ns logic, 2.600ns route) (28.5% logic, 71.5% route) -------------------------------------------------------------------------------- Slack (setup path): 27.765ns (requirement - (data path - clock path skew + uncertainty)) Source: count_10 (FF) Destination: count_7 (FF) Requirement: 31.250ns Data Path Delay: 3.433ns (Levels of Logic = 2) Clock Path Skew: -0.017ns (0.283 - 0.300) Source Clock: CLK_BUFGP rising at 0.000ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: count_10 to count_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y40.CQ Tcko 0.430 count<11> count_10 SLICE_X14Y41.B1 net (fanout=3) 1.136 count<10> SLICE_X14Y41.B Tilo 0.235 LED1_OBUF count[26]_GND_1_o_equal_2_o<26>4 SLICE_X13Y39.D2 net (fanout=19) 1.259 count[26]_GND_1_o_equal_2_o<26>3 SLICE_X13Y39.CLK Tas 0.373 count<7> count_7_rstpot count_7 ------------------------------------------------- --------------------------- Total 3.433ns (1.038ns logic, 2.395ns route) (30.2% logic, 69.8% route) -------------------------------------------------------------------------------- Slack (setup path): 27.953ns (requirement - (data path - clock path skew + uncertainty)) Source: count_11 (FF) Destination: count_7 (FF) Requirement: 31.250ns Data Path Delay: 3.245ns (Levels of Logic = 2) Clock Path Skew: -0.017ns (0.283 - 0.300) Source Clock: CLK_BUFGP rising at 0.000ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: count_11 to count_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y40.DQ Tcko 0.430 count<11> count_11 SLICE_X14Y41.B2 net (fanout=3) 0.948 count<11> SLICE_X14Y41.B Tilo 0.235 LED1_OBUF count[26]_GND_1_o_equal_2_o<26>4 SLICE_X13Y39.D2 net (fanout=19) 1.259 count[26]_GND_1_o_equal_2_o<26>3 SLICE_X13Y39.CLK Tas 0.373 count<7> count_7_rstpot count_7 ------------------------------------------------- --------------------------- Total 3.245ns (1.038ns logic, 2.207ns route) (32.0% logic, 68.0% route) -------------------------------------------------------------------------------- Paths for end point count_23 (SLICE_X13Y41.A1), 24 paths -------------------------------------------------------------------------------- Slack (setup path): 27.618ns (requirement - (data path - clock path skew + uncertainty)) Source: count_1 (FF) Destination: count_23 (FF) Requirement: 31.250ns Data Path Delay: 3.580ns (Levels of Logic = 7) Clock Path Skew: -0.017ns (0.285 - 0.302) Source Clock: CLK_BUFGP rising at 0.000ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: count_1 to count_23 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y38.BQ Tcko 0.430 count<3> count_1 SLICE_X12Y38.B1 net (fanout=3) 0.730 count<1> SLICE_X12Y38.COUT Topcyb 0.483 Mcount_count_cy<3> Mcount_count_lut<1>_INV_0 Mcount_count_cy<3> SLICE_X12Y39.CIN net (fanout=1) 0.003 Mcount_count_cy<3> SLICE_X12Y39.COUT Tbyp 0.093 Mcount_count_cy<7> Mcount_count_cy<7> SLICE_X12Y40.CIN net (fanout=1) 0.082 Mcount_count_cy<7> SLICE_X12Y40.COUT Tbyp 0.093 Mcount_count_cy<11> Mcount_count_cy<11> SLICE_X12Y41.CIN net (fanout=1) 0.003 Mcount_count_cy<11> SLICE_X12Y41.COUT Tbyp 0.093 Mcount_count_cy<15> Mcount_count_cy<15> SLICE_X12Y42.CIN net (fanout=1) 0.003 Mcount_count_cy<15> SLICE_X12Y42.COUT Tbyp 0.093 Mcount_count_cy<19> Mcount_count_cy<19> SLICE_X12Y43.CIN net (fanout=1) 0.003 Mcount_count_cy<19> SLICE_X12Y43.DMUX Tcind 0.320 Result<23> Mcount_count_xor<23> SLICE_X13Y41.A1 net (fanout=1) 0.778 Result<23> SLICE_X13Y41.CLK Tas 0.373 count<23> count_23_rstpot count_23 ------------------------------------------------- --------------------------- Total 3.580ns (1.978ns logic, 1.602ns route) (55.3% logic, 44.7% route) -------------------------------------------------------------------------------- Slack (setup path): 27.628ns (requirement - (data path - clock path skew + uncertainty)) Source: count_0 (FF) Destination: count_23 (FF) Requirement: 31.250ns Data Path Delay: 3.570ns (Levels of Logic = 7) Clock Path Skew: -0.017ns (0.285 - 0.302) Source Clock: CLK_BUFGP rising at 0.000ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: count_0 to count_23 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y38.AQ Tcko 0.430 count<3> count_0 SLICE_X12Y38.A2 net (fanout=3) 0.729 count<0> SLICE_X12Y38.COUT Topcya 0.474 Mcount_count_cy<3> count<0>_rt Mcount_count_cy<3> SLICE_X12Y39.CIN net (fanout=1) 0.003 Mcount_count_cy<3> SLICE_X12Y39.COUT Tbyp 0.093 Mcount_count_cy<7> Mcount_count_cy<7> SLICE_X12Y40.CIN net (fanout=1) 0.082 Mcount_count_cy<7> SLICE_X12Y40.COUT Tbyp 0.093 Mcount_count_cy<11> Mcount_count_cy<11> SLICE_X12Y41.CIN net (fanout=1) 0.003 Mcount_count_cy<11> SLICE_X12Y41.COUT Tbyp 0.093 Mcount_count_cy<15> Mcount_count_cy<15> SLICE_X12Y42.CIN net (fanout=1) 0.003 Mcount_count_cy<15> SLICE_X12Y42.COUT Tbyp 0.093 Mcount_count_cy<19> Mcount_count_cy<19> SLICE_X12Y43.CIN net (fanout=1) 0.003 Mcount_count_cy<19> SLICE_X12Y43.DMUX Tcind 0.320 Result<23> Mcount_count_xor<23> SLICE_X13Y41.A1 net (fanout=1) 0.778 Result<23> SLICE_X13Y41.CLK Tas 0.373 count<23> count_23_rstpot count_23 ------------------------------------------------- --------------------------- Total 3.570ns (1.969ns logic, 1.601ns route) (55.2% logic, 44.8% route) -------------------------------------------------------------------------------- Slack (setup path): 27.639ns (requirement - (data path - clock path skew + uncertainty)) Source: count_5 (FF) Destination: count_23 (FF) Requirement: 31.250ns Data Path Delay: 3.561ns (Levels of Logic = 6) Clock Path Skew: -0.015ns (0.285 - 0.300) Source Clock: CLK_BUFGP rising at 0.000ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: count_5 to count_23 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y39.BQ Tcko 0.430 count<7> count_5 SLICE_X12Y39.B1 net (fanout=3) 0.807 count<5> SLICE_X12Y39.COUT Topcyb 0.483 Mcount_count_cy<7> Mcount_count_lut<5>_INV_0 Mcount_count_cy<7> SLICE_X12Y40.CIN net (fanout=1) 0.082 Mcount_count_cy<7> SLICE_X12Y40.COUT Tbyp 0.093 Mcount_count_cy<11> Mcount_count_cy<11> SLICE_X12Y41.CIN net (fanout=1) 0.003 Mcount_count_cy<11> SLICE_X12Y41.COUT Tbyp 0.093 Mcount_count_cy<15> Mcount_count_cy<15> SLICE_X12Y42.CIN net (fanout=1) 0.003 Mcount_count_cy<15> SLICE_X12Y42.COUT Tbyp 0.093 Mcount_count_cy<19> Mcount_count_cy<19> SLICE_X12Y43.CIN net (fanout=1) 0.003 Mcount_count_cy<19> SLICE_X12Y43.DMUX Tcind 0.320 Result<23> Mcount_count_xor<23> SLICE_X13Y41.A1 net (fanout=1) 0.778 Result<23> SLICE_X13Y41.CLK Tas 0.373 count<23> count_23_rstpot count_23 ------------------------------------------------- --------------------------- Total 3.561ns (1.885ns logic, 1.676ns route) (52.9% logic, 47.1% route) -------------------------------------------------------------------------------- Hold Paths: NET "CLK_BUFGP/IBUFG" PERIOD = 31.25 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point LED1 (SLICE_X14Y41.A6), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.418ns (requirement - (clock path skew + uncertainty - data path)) Source: LED1 (FF) Destination: LED1 (FF) Requirement: 0.000ns Data Path Delay: 0.418ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: CLK_BUFGP rising at 31.250ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: LED1 to LED1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X14Y41.AQ Tcko 0.200 LED1_OBUF LED1 SLICE_X14Y41.A6 net (fanout=2) 0.028 LED1_OBUF SLICE_X14Y41.CLK Tah (-Th) -0.190 LED1_OBUF LED1_rstpot LED1 ------------------------------------------------- --------------------------- Total 0.418ns (0.390ns logic, 0.028ns route) (93.3% logic, 6.7% route) -------------------------------------------------------------------------------- Paths for end point count_12 (SLICE_X15Y41.A6), 6 paths -------------------------------------------------------------------------------- Slack (hold path): 0.689ns (requirement - (clock path skew + uncertainty - data path)) Source: count_14 (FF) Destination: count_12 (FF) Requirement: 0.000ns Data Path Delay: 0.689ns (Levels of Logic = 2) Clock Path Skew: 0.000ns Source Clock: CLK_BUFGP rising at 31.250ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: count_14 to count_12 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X15Y41.DQ Tcko 0.198 count<14> count_14 SLICE_X14Y41.C6 net (fanout=3) 0.032 count<14> SLICE_X14Y41.C Tilo 0.142 LED1_OBUF count[26]_GND_1_o_equal_2_o<26>1 SLICE_X15Y41.A6 net (fanout=13) 0.102 count[26]_GND_1_o_equal_2_o<26> SLICE_X15Y41.CLK Tah (-Th) -0.215 count<14> count_12_rstpot count_12 ------------------------------------------------- --------------------------- Total 0.689ns (0.555ns logic, 0.134ns route) (80.6% logic, 19.4% route) -------------------------------------------------------------------------------- Slack (hold path): 0.829ns (requirement - (clock path skew + uncertainty - data path)) Source: count_17 (FF) Destination: count_12 (FF) Requirement: 0.000ns Data Path Delay: 0.829ns (Levels of Logic = 2) Clock Path Skew: 0.000ns Source Clock: CLK_BUFGP rising at 31.250ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: count_17 to count_12 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X15Y42.CQ Tcko 0.198 count<18> count_17 SLICE_X14Y41.C5 net (fanout=3) 0.172 count<17> SLICE_X14Y41.C Tilo 0.142 LED1_OBUF count[26]_GND_1_o_equal_2_o<26>1 SLICE_X15Y41.A6 net (fanout=13) 0.102 count[26]_GND_1_o_equal_2_o<26> SLICE_X15Y41.CLK Tah (-Th) -0.215 count<14> count_12_rstpot count_12 ------------------------------------------------- --------------------------- Total 0.829ns (0.555ns logic, 0.274ns route) (66.9% logic, 33.1% route) -------------------------------------------------------------------------------- Slack (hold path): 0.881ns (requirement - (clock path skew + uncertainty - data path)) Source: count_15 (FF) Destination: count_12 (FF) Requirement: 0.000ns Data Path Delay: 0.881ns (Levels of Logic = 2) Clock Path Skew: 0.000ns Source Clock: CLK_BUFGP rising at 31.250ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: count_15 to count_12 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X15Y42.AQ Tcko 0.198 count<18> count_15 SLICE_X14Y41.C4 net (fanout=3) 0.224 count<15> SLICE_X14Y41.C Tilo 0.142 LED1_OBUF count[26]_GND_1_o_equal_2_o<26>1 SLICE_X15Y41.A6 net (fanout=13) 0.102 count[26]_GND_1_o_equal_2_o<26> SLICE_X15Y41.CLK Tah (-Th) -0.215 count<14> count_12_rstpot count_12 ------------------------------------------------- --------------------------- Total 0.881ns (0.555ns logic, 0.326ns route) (63.0% logic, 37.0% route) -------------------------------------------------------------------------------- Paths for end point LED1 (SLICE_X14Y41.A1), 6 paths -------------------------------------------------------------------------------- Slack (hold path): 0.812ns (requirement - (clock path skew + uncertainty - data path)) Source: count_14 (FF) Destination: LED1 (FF) Requirement: 0.000ns Data Path Delay: 0.814ns (Levels of Logic = 2) Clock Path Skew: 0.002ns (0.033 - 0.031) Source Clock: CLK_BUFGP rising at 31.250ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: count_14 to LED1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X15Y41.DQ Tcko 0.198 count<14> count_14 SLICE_X14Y41.C6 net (fanout=3) 0.032 count<14> SLICE_X14Y41.C Tilo 0.142 LED1_OBUF count[26]_GND_1_o_equal_2_o<26>1 SLICE_X14Y41.A1 net (fanout=13) 0.252 count[26]_GND_1_o_equal_2_o<26> SLICE_X14Y41.CLK Tah (-Th) -0.190 LED1_OBUF LED1_rstpot LED1 ------------------------------------------------- --------------------------- Total 0.814ns (0.530ns logic, 0.284ns route) (65.1% logic, 34.9% route) -------------------------------------------------------------------------------- Slack (hold path): 0.954ns (requirement - (clock path skew + uncertainty - data path)) Source: count_17 (FF) Destination: LED1 (FF) Requirement: 0.000ns Data Path Delay: 0.954ns (Levels of Logic = 2) Clock Path Skew: 0.000ns Source Clock: CLK_BUFGP rising at 31.250ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: count_17 to LED1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X15Y42.CQ Tcko 0.198 count<18> count_17 SLICE_X14Y41.C5 net (fanout=3) 0.172 count<17> SLICE_X14Y41.C Tilo 0.142 LED1_OBUF count[26]_GND_1_o_equal_2_o<26>1 SLICE_X14Y41.A1 net (fanout=13) 0.252 count[26]_GND_1_o_equal_2_o<26> SLICE_X14Y41.CLK Tah (-Th) -0.190 LED1_OBUF LED1_rstpot LED1 ------------------------------------------------- --------------------------- Total 0.954ns (0.530ns logic, 0.424ns route) (55.6% logic, 44.4% route) -------------------------------------------------------------------------------- Slack (hold path): 1.006ns (requirement - (clock path skew + uncertainty - data path)) Source: count_15 (FF) Destination: LED1 (FF) Requirement: 0.000ns Data Path Delay: 1.006ns (Levels of Logic = 2) Clock Path Skew: 0.000ns Source Clock: CLK_BUFGP rising at 31.250ns Destination Clock: CLK_BUFGP rising at 31.250ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: count_15 to LED1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X15Y42.AQ Tcko 0.198 count<18> count_15 SLICE_X14Y41.C4 net (fanout=3) 0.224 count<15> SLICE_X14Y41.C Tilo 0.142 LED1_OBUF count[26]_GND_1_o_equal_2_o<26>1 SLICE_X14Y41.A1 net (fanout=13) 0.252 count[26]_GND_1_o_equal_2_o<26> SLICE_X14Y41.CLK Tah (-Th) -0.190 LED1_OBUF LED1_rstpot LED1 ------------------------------------------------- --------------------------- Total 1.006ns (0.530ns logic, 0.476ns route) (52.7% logic, 47.3% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: NET "CLK_BUFGP/IBUFG" PERIOD = 31.25 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 28.584ns (period - min period limit) Period: 31.250ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) Physical resource: CLK_BUFGP/BUFG/I0 Logical resource: CLK_BUFGP/BUFG/I0 Location pin: BUFGMUX_X2Y2.I0 Clock network: CLK_BUFGP/IBUFG -------------------------------------------------------------------------------- Slack: 30.775ns (period - min period limit) Period: 31.250ns Min period limit: 0.475ns (2105.263MHz) (Tcp) Physical resource: LED1_OBUF/CLK Logical resource: LED1/CK Location pin: SLICE_X14Y41.CLK Clock network: CLK_BUFGP -------------------------------------------------------------------------------- Slack: 30.780ns (period - min period limit) Period: 31.250ns Min period limit: 0.470ns (2127.660MHz) (Tcp) Physical resource: count<3>/CLK Logical resource: count_0/CK Location pin: SLICE_X13Y38.CLK Clock network: CLK_BUFGP -------------------------------------------------------------------------------- All constraints were met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Clock to Setup on destination clock CLK ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ CLK | 3.695| | | | ---------------+---------+---------+---------+---------+ Timing summary: --------------- Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) Constraints cover 901 paths, 0 nets, and 211 connections Design statistics: Minimum period: 3.695ns{1} (Maximum frequency: 270.636MHz) ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. Analysis completed Tue Feb 21 22:17:03 2017 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 390 MB