led Project Status (02/21/2017 - 22:10:44)
Project File: FPGA-led-lights.xise Parser Errors: No Errors
Module Name: led Implementation State: Programming File Generated
Target Device: xc6slx9-2tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
98 Warnings (2 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 25 11,440 1%  
    Number used as Flip Flops 25      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 57 5,720 1%  
    Number used as logic 57 5,720 1%  
        Number using O6 output only 34      
        Number using O5 output only 1      
        Number using O5 and O6 22      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
Number of occupied Slices 15 1,430 1%  
Number of MUXCYs used 24 2,860 1%  
Number of LUT Flip Flop pairs used 57      
    Number with an unused Flip Flop 32 57 56%  
    Number with an unused LUT 0 57 0%  
    Number of fully used LUT-FF pairs 25 57 43%  
    Number of unique control sets 1      
    Number of slice register sites lost
        to control set restrictions
7 11,440 1%  
Number of bonded IOBs 2 102 1%  
    Number of LOCed IOBs 2 2 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.24      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Feb 21 22:10:17 201703 Warnings (2 new)0
Translation ReportCurrentTue Feb 21 22:16:44 2017095 Warnings (0 new)207 Infos (0 new)
Map ReportCurrentTue Feb 21 22:16:54 2017008 Infos (0 new)
Place and Route ReportCurrentTue Feb 21 22:16:59 2017000
Power Report     
Post-PAR Static Timing ReportCurrentTue Feb 21 22:17:03 2017003 Infos (0 new)
Bitgen ReportCurrentTue Feb 21 22:17:08 2017000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentTue Feb 21 22:17:09 2017
WebTalk Log FileCurrentTue Feb 21 22:17:10 2017

Date Generated: 02/21/2017 - 23:44:54