Project Statistics |
PROPEXT_xilxSynthMaxFanout_virtex2=100000 |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_ProjectDescription=This is a project that will make patterns with led lights. |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2017-02-19T23:09:37 |
PROP_intWbtProjectID=8C4A34387ED46BFEECE9D369B6F8AAAE |
PROP_intWbtProjectIteration=19 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxBitgStart_IntDone=true |
PROP_xilxNgdbld_AUL=true |
PROP_AutoTop=true |
PROP_DevFamily=Spartan6 |
PROP_DevDevice=xc6slx9 |
PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=tqg144 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-2 |
PROP_PreferredLanguage=Verilog |
FILE_UCF=1 |
FILE_VERILOG=1 |