From 2ba9d114765aa1b50e5a7dd8ae3511af08dbf1eb Mon Sep 17 00:00:00 2001
From: Yann Herklotz <ymherklotz@gmail.com>
Date: Tue, 15 Nov 2016 21:51:17 +0000
Subject: Create README.md

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+# Experiment VERI: FPGA Design with Verilog (Part 1)
+In this experiment we will be programming a Cyclone V FPGA from Altera on a DE1-SoC Board that was made by Terasicas
+We will minsdawdaw
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cgit